TM4C129 configure the stall count for EPI HB16 iRDY

int main(void) {
	//desired system frequency
	gSysCtlClock = SysCtlClockFreqSet(
						SYSCTL_USE_PLL    |
						SYSCTL_OSC_MAIN   |
						SYSCTL_XTAL_25MHZ |
						SYSCTL_CFG_VCO_480,
						120000000);


	SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
	SysCtlPeripheralReset(SYSCTL_PERIPH_EPI0);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOA);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOB);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOC);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOD);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOE);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOF);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOG);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOH);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOJ);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOK);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOL);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOM);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPION);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOP);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOQ);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOR);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOS);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);
	SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOT);

	GPIOPinConfigure(GPIO_PK5_EPI0S31); //EPI CLK
	GPIOPinConfigure(GPIO_PP3_EPI0S30); //EPI ALE/HAS
	GPIOPinConfigure(GPIO_PP2_EPI0S29); //EPI WR
	GPIOPinConfigure(GPIO_PB3_EPI0S28); //EPI RD
	GPIOPinConfigure(GPIO_PK4_EPI0S32); //EPI RDY
	GPIOPinConfigure(GPIO_PL0_EPI0S16); //EPI A0/HHWIL
	GPIOPinConfigure(GPIO_PK0_EPI0S0);  //EPI D0
	GPIOPinConfigure(GPIO_PK1_EPI0S1);  //EPI D1
	GPIOPinConfigure(GPIO_PK2_EPI0S2);  //EPI D2
	GPIOPinConfigure(GPIO_PK3_EPI0S3);  //EPI D3
	GPIOPinConfigure(GPIO_PC7_EPI0S4);  //EPI D4
	GPIOPinConfigure(GPIO_PC6_EPI0S5);  //EPI D5
	GPIOPinConfigure(GPIO_PC5_EPI0S6);  //EPI D6
	GPIOPinConfigure(GPIO_PC4_EPI0S7);  //EPI D7
	GPIOPinConfigure(GPIO_PA6_EPI0S8);  //EPI D8
	GPIOPinConfigure(GPIO_PA7_EPI0S9);  //EPI D9
	GPIOPinConfigure(GPIO_PG1_EPI0S10); //EPI D10
	GPIOPinConfigure(GPIO_PG0_EPI0S11); //EPI D11
	GPIOPinConfigure(GPIO_PM3_EPI0S12); //EPI D12
	GPIOPinConfigure(GPIO_PM2_EPI0S13); //EPI D13
	GPIOPinConfigure(GPIO_PM1_EPI0S14); //EPI D14
	GPIOPinConfigure(GPIO_PM0_EPI0S15); //EPI D15

	GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0 |	//EPI D0
									GPIO_PIN_1 |	//EPI D1
									GPIO_PIN_2 |	//EPI D2
									GPIO_PIN_3);	//EPI D3
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7 |	//EPI D4
									GPIO_PIN_6 |	//EPI D5
									GPIO_PIN_5 |	//EPI D6
									GPIO_PIN_4);	//EPI D7
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6 |	//EPI D8
									GPIO_PIN_7);	//EPI D9
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1 |	//EPI D10
									GPIO_PIN_0);	//EPI D11
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3 |	//EPI D12
									GPIO_PIN_2 |	//EPI D13
									GPIO_PIN_1 |	//EPI D14
									GPIO_PIN_0);	//EPI D15
	GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);	//EPI RD
	GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2 |	//EPI WR
									GPIO_PIN_3);	//EPI ALE
	GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_4 |	//EPI IRDY
									GPIO_PIN_5);	//EPI CLOCK
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);	//EPI A0/HHWIL






	// Set pointer to EPI memory mapped window.
	g_pusEPIFPGA = (uint16_t *)0xC0000000;

	//reset the EPI interface
	EPIModeSet(			EPI0_BASE,
						EPI_MODE_DISABLE);

	// Set the EPI divider.
	EPIDividerSet(		EPI0_BASE,
						EPI_DIV_FACTOR_DATA);

	//enable the EPI interface, and use general purpose mode
	EPIModeSet(			EPI0_BASE,
						EPI_MODE_HB16);
    EPIConfigHB16Set(	EPI0_BASE,
//						EPI_HB16_IN_READY_EN          |  	//IRDY enabled
						EPI_HB16_MODE_ADDEMUX         | 	//sets up data and address as separate
						EPI_HB16_CSCFG_ALE            |		//EPIS030 to operate as an address latch (ALE)
						EPI_HB16_ALE_HIGH             |		//sets the address latch active high
						EPI_HB16_WRWAIT_0             |		//sets write wait state to 2 EPI clocks.
						EPI_HB16_RDWAIT_0             , 	//sets read wait state to 2 EPI clocks.
						1);									//FIFO mode	maximum number of clocks
	EPIConfigHB16TimingSet(EPI0_BASE,
						0			,						//specifies the chip select to configure[0-3]
						EPI_HB16_IN_READY_DELAY_1     |   	//sets the stall on input ready (EPIS032)
															//to start 1 EPI clock after signaled
						EPI_HB16_WRWAIT_MINUS_ENABLE  |		//enables a 1 EPI clock write wait state reduction
						EPI_HB16_RDWAIT_MINUS_ENABLE); 		//enables a 1 EPI clock read wait state reduction

	//setup the address mapping for low level driver
	//  - EPI_HPI_read( )
	//  - EPI_HPI_write( )
	//Note: for some reason if the Epi Rx FIFO trigger level is more
	//		than 1/8, the FIRST word has always a wrong values.
	EPIAddressMapSet(	EPI0_BASE,
						EPI_ADDR_PER_BASE_C   |
						EPI_ADDR_PER_SIZE_64KB);
	EPIFIFOConfig(		EPI0_BASE,
						EPI_FIFO_CONFIG_TX_1_4 |
						EPI_FIFO_CONFIG_RX_1_8);

	//configure the EPI Non blocking read
	EPINonBlockingReadConfigure(EPI0_BASE,
								0,
								EPI_NBCONFIG_SIZE_16,
								0);











	//read from the EPI interface
	while(1) {
		g_pusEPIFPGA = (uint16_t *)0xC0000000;

		for(i = 0; i < 10; i++) {
			word  = (uint32_t) *g_pusEPIFPGA;		//read lower 16bits
			g_pusEPIFPGA++;
			word |= (uint32_t) *g_pusEPIFPGA << 16;	//read upper 16bits
			g_pusEPIFPGA++;

			u32DataIn[i] = word;
		}//for loop
	}//while(1)
}//main