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Can the cache maintenance instructions be used on Cortex-R5?

Christian Herget
Expert 6985 points
Other Parts Discussed in Thread: TMS570LC4357, RM57L843

Hi,

I read in the Cortex-R5 TRM that the CPU supports cache maintenance instructions like ICIMVAU, DCIMVAC, DCCMVAC and DCCIMVAC (Chapter 4.3.22).

I wonder if these can be used on RM57 or TMS570LC4357 to selectively invalidate the cache in case for example the Flash was partially re written, or if it is necessary to always invalidate the entire Data or Instruction cache in case the flash content has been changed?

Thanks,
Christian

  • 0
    TI__Guru 72500 points
    The operations described in section 4.3.22 of the Cortex R5 TRM are supported by the R5 in the RM57L843 and the TMS570LC4357, but the mnemonics are not supported by the TI assembler. They would have to be encoded using co-processor instructions.
  • 0 in reply to Bob Crosby
    TI__Expert 6985 points
    Hi Bob,

    Thanks for confirming that these will work on our R5 implementation.

    I will try the following "instructions":

    /* ICIMVAU, Invalidate Instruction Cache Line by MVA to PoU */
    __inline void coreICIMVAU(uint32_t u32address)
    {
    /* CRn Opcode_1 CRm Opcode_2 */
    /* c7 0 c5 1 */
    __MCR(15, 0, u32address, 7, 5, 1);
    }

    /* DCIMVAC, Invalidate data cache line by MVA to PoC */
    __inline void coreDCIMVAC(uint32_t u32address)
    {
    /* CRn Opcode_1 CRm Opcode_2 */
    /* c7 0 c6 1 */
    __MCR(15, 0, u32address, 7, 6, 1);
    }

    /* DCCMVAC, Clean data cache line by MVA to PoC */
    __inline void coreDCCMVAC(uint32_t u32address)
    {
    /* CRn Opcode_1 CRm Opcode_2 */
    /* c7 0 c10 1 */
    __MCR(15, 0, u32address, 7, 10, 1);
    }

    /* DCCIMVAC, Clean and invalidate data cache line by MVA to PoC */
    __inline void coreDCCIMVAC(uint32_t u32address)
    {
    /* CRn Opcode_1 CRm Opcode_2 */
    /* c7 0 c14 1 */
    __MCR(15, 0, u32address, 7, 14, 1);
    }

    Best Regards,
    Christian