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TMS470MF03107 and FreeRTOS: Interrupt Prioritization...

Amanda Ross95
Intellectual 2740 points
Other Parts Discussed in Thread: TMS470MF03107

Hello,

My customer is running FreeRTOS on their TMS470MF03107 and is using a FreeRTOS port for MCUs based on the ARM M3, This FreeRTOS port disables interrupts by writing to the M3 BASEPRI register to raise the CPU priority above peripheral interrupt priorities (by writing a lower priority value). Yet the following statement is made on page 283 of the TMS470M's TRM - 

'Note: It is not recommended to modify the NVIC BASEPRI or PRIMASK registers during normal operation. Modifying these registers may result in loss of M3VIM - NVIC synchronization and unpredictable system behavior.'

Given the fact that they're just using writes to the BASEPRI register to adjust CPU priority, will they also see this nuances in system behavior and do you have any sense (besides the loss of synchronization) for how the behavior might manifest itself?

Our question after that would be, are you familiar with any other customers who are also running FreeRTOS on TMS470M series MCUs and if so, what strategy are they using to mask interrupts besides needing to modify the BASEPRI register?

Any feedback you can provide is deeply appreciated.

Thanks so much for your time,

-Amanda

  • 0
    TI__Guru 72500 points
    Hi Amanda,

    I am forwarding this to someone who knows more about the M3 architecture than me.
  • 0
    TI__Guru 59540 points
    Hello Amanda,

    To begin it is important to understand that when we developed the TMS470M devices we were coming from the ARM7TDMI core and wanted to maintain some level of SW compatibility to prior devices. This gets back to our customer's SW investment. In order to keep some level of compatibility in the way interrupts were handled, we built the M3VIM on top of the NVIC so that legacy SW could be easily ported to the M3 devices. In doing so, we made it somewhat important leave the NVIC alone and utilize the M3VIM exclusively for interrupt management. This is where the recommendations for leaving the BASEPRI and PRIMASK alone comes from.

    In regard to what types of behavior can be expected if the BASEPRI and PRIMASK registers are modified, I can't really state anything different than what is stated in the TRM in that the behavior will be unpredictable or indeterminate. This is because it was not tested in simulation or in silicon due to the number of possible permutations of the values written into BASEPRI and PRIMASK.

    If there is a desire to modify interrupt priority or disable interrupts, it should be done through the M3VIM which provides mechanisms for this aside from the NMI interrupt. I would encourage you to review chapter 8 of the TRM for details on the M3VIM and it's use.

    Finally, I am not aware of any others using FreeRTOS with the TMS470M devices but do know of customers that have used other RTOS implementations. Again, I believe the necessary functionality should be achievable with the M3VIM without writing to the BASEPRI or PRIMASK registers.

    Let me know if there are any additional questions.
  • 0 in reply to Chuck Davenport
    TI__Intellectual 2740 points
    Thank you for your response Chuck and thank you Bob for the direction!

    -Amanda
  • 0 in reply to Chuck Davenport
    TI__Intellectual 2740 points
    One last quick question! The FreeRTOS code they're currently using employs the SysTick feature of the NVIC. If they avoid using BASEPRI and PRIMASK register, then they can only disable the SysTick interrupt by clearing the TICKINT bit in the SysTick Control and Status register. Is there any chance that writing to that register could cause issues with the M3VIM/NVIC integration?
  • 0 in reply to Amanda Ross95
    TI__Guru 59540 points
    Hello Amanda,

    I'm not sure what affect writing to the SysTick control register would have. I don't recall any notifications or indications from the design team about it and it is located at the NVIC vector table offset 0x3C where the M3VIM starts at 0x40 so I don't believe there will be any interference/priority issues. With that said, an alternative would be to use the RTI as the system tick/loop counter if the RTOS systick code can be adapted or demonstrates unexpected behaviors.
  • 0 in reply to Chuck Davenport
    TI__Intellectual 2740 points
    Thank you again Chuck, this has been very helpful to the customer.

    -Amanda