RM44L520: DCC module: HALCoGen generated code & TRM weird description

Hello

According to your application report regarding DCC: www.ti.com/.../spna211.pdf

I have clk0 = OSCIN (16MHz), clk1 = EXTCLKIN (10MHz)

Minimum valid in case is therefore equation 3 from the application note because clk0 Freq > clk1 Freq.

Assuming "TclockX" == time of the clock period, not frequency of the clock (10Mhz clk --> 1/10000000=100ns)... "Tclock" syntax is not opened anywhere but example in chapter 5 selects equation 2 when clock freqs are opposite way.

Valid(min) = 2*(2*(Tclk1/Tclk0)+3) ==> 2*(2*((1/10) / (1/16))+3) => 2*(2*(16/10)+3) => 2*(2*1,6+3) => 2*(3,2+3) => 2*6,2 = 12,4. Assuming integer is needed so therefore Valid(min) >= 13?

Question 1: was above calculation correct, so with my setup the Valid(min) needs to be at least 13?

Question 2: If above is correct why HalCoGen lets me select & generate code where Valid(min) goes below that limit? It doesnt give warning or anything like it gives if allowed drift is set to 0%...

If I set maximum time to 500us then Valid is 2 and HalcoGen says that "DCC1 VALID0 is too small, try increasing or reducing the allowed percentage of error"

With 700us the valid is 4 and HalCogen is again happy...

By calculating other way around just to double check HalCogen "warning" 2*(2*10/16+3) == 8,5. And equation 2 gives 10 (if used wrong equation). Any of the value 8,5 / 10 / 12,4 are above 4 and still that 4 is ok for HalCoGen, why only value 2 for valid throws warning?

Question 3: Should I manually tune Allowed drift / detection in order to meet Valid(min) calculated above (13)? So 0,02% and 2200usec would give 14.

Question 4: TRM in figure 11-1 states that DCC has 3 outputs (error/done/reload).  Table 11-2 states that error interrupt is generated if ERR_ENA is set. That interrupt must be ESM module channel 30 for DCC1 (because DCC module does not have error interrupt in VIM table) and I tested that ESM does not give interrupt if ERR_ENA is not set and gives if set (Table 11-2 text is very misleading, at first it looks like DCC module gives IRQ like it generates done interrupt).

How ever this also speaks only about interrupt but ESM module can be configured to control also ERROR_PIN or only pin when ch30 activates and Figure 11-1 has only 1 output to ESM module. Haven't tested but based on the ESM module description and figure 11-1 this Table 11-2 ERR_ENA bit must also affect the ESM module ERROR_PIN control.  Nothing has been said in TRM about that. If that ERR_ENA relates also to ERROR_PIN control table 11-2 should state "signal to ESM, refer ESM module how to select what happens in DCC error event" and nothing about interrupt because that is ESM module logic where DCC module cannot affect...