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Hi!
I think the HALCoGen FreeRTOS template for chip RM44L520PGE is wrong.
Update: Most of my issues were related to my own project configurations.
Problem
On my system the timing is all arbitrary, e.g. the ECLK signal is unstable.
Edit: The PINMUX tab is for a different type of packaging.
Setup project setup
HALCoGen version 04.07.00
IAR EWARM FS version 7.40.x
Chip: RM44L520PGE on custom hardware
Debugger: JLink Plus
Logic Analyzer: Saleae Logic Pro 16
Comparison project setup
HALCoGen version 04.07.00
IAR EWARM FS version 7.40.x
Chip: RM44L520PGE on XL2-RM46 Launchpad
Debugger: JLink Plus
Logic Analyzer: Saleae Logic Pro 16
Symptoms:
* The ECLK signal is all wrong. It looks like it's "trying" to output the expected frequency, but something's messing with it.
* Trying to use the vTaskDelayUntil() function in FreeRTOS, which should provide periodic behaviour, has too low periods and has a lot of jitter.
* When I close the IDE debugging session, the behaviour changes.
* If I run the same project with the same HALCoGen source code, create a task and start the scheduler but never invoke vTaskDelayUntil(), the ECLK signal is just fine.
Comparison: Running FreeRTOS on the XL2-RM46 shows none of these problems. ECLK is stable (shows up on my analyzer as flawless on 10 MHz, shows up with some jitter on 40 MHz)
Suspected cause:
* Some of the driver templates in the HALCoGen appears to have been copypasted from RM44L522ZWT_FREERTOS to RM44L520PGE_FREERTOS without making any corrections. For example the PINMUX tab is for the wrong type of packaging.
Other possible causes:
* Using IAR instead of CCS
* Flaws in our hardware.
* Some configuration difference between the two projects I haven't noticed
* Me.
Conclusion
There is probably something wrong with the configuration template for RM44L520PGE_FREERTOS
//Audun