TMDXRM57LHDK: Receiving data on SCI3 using DMA

Hello Julio,

I am looking into your question and will get back with you on this tomorrow. Apologies for the delay.

Hi Chuck,

thanks for helping on this thread too.
Were you able to find something?

Best regards,
Julio

Julio,

I do apologize for the continued delay. I am hopeful to get to this tomorrow.

Julio,

To start, I apologize for the delay in getting back with you.

Julio Cesar Aguilar Zerpa said:

I found the sci dma example (Halcogen), but I can't get it to work. It prints FAIL in loopback mode or gets stuck in the while loop when loopback is zero. 

I created a new project, enabled sci3 and sci4 in Halcogen, didn't change the configuration (all sci interrupts disabled, frame parameters in both is the same), and generated the code.

Am I missing some configuration steps? 

I am not certain if all steps have been included based solely on your statement above. I think that you have most likely configured the HalCoGen tool correctly but without also seeing the code, it won't be possible to see if the DMA is configured as it should. Of key interest is configuration of which SCI to read from.

Julio Cesar Aguilar Zerpa said:

Another thing is: according to some other forum threads, if DMA is to be used to receive data, a dummy DMA transfer needs to be implemented to update the CTCOUNT, which allows to trigger again the DMA receive request. So I guess, I am going to need that. 

What would be the dummy_req_line that should be used in 'dmaReqAssign(DMA_CHX, dummy_req_line)', if my dummy send and receive buffers are defined in my application (uint8 dummy_array[2], where idx 0 would be the tx addrs and idx 1 the rx addrs)?

For the Dummy read will be needed. I think, since you are using the SCI in just a receive mode (half-duplex) that you should be able to initiate a transmit in loop back mode during initialization. When the dummy data is received, it can be thrown out. At that point, the DMA should be able to take over.

I also found and application note covering SCI with DMA that may be of help to you. It is located here www.ti.com/.../spna213.pdf.

Hi Chuck,

again thanks for the help. It was the cache settings.

The example is now working but only in loopback mode. If loopback mode is set to false, the program hangs in the while loop. I'll see what I can find.

I'm attaching the halcogen files. Maybe they help you find some other error.

2766.SciDmaTransfer.zip

Edit:

I just realized that it can't work when loopback mode is zero without an external source attached to the SCI4.

Thanks.

Best regards,
Julio

Hi Chuck,

I am trying to understand the example to apply it in my application.

I need to receive serial data over DMA triggered by HW, but as mentioned before I need to constantly (or after each SCI DMA RX) trigger a dummy dma request so that future SCI DMA RX requests can be triggered.

I am trying to trigger the loopback mode DMA transfers (TX and RX) from the example constantly but it is not working. I just get the first transfer. Afterwards, the program stays in the 'while(dmaGetInterruptStatus(DMA_CH2, BTC) != TRUE)'.

I don't know which function does the actual triggering. I've even used the whole code in a loop and nothing. I just get the first transfer.

What do I have to set?

Btw, I didn't understand what you said about doing a transfer in loopback mode as initialization and that should trigger my dma_sci_rx request.

Best regards,
Julio

Julio Cesar Aguilar Zerpa said:

I need to receive serial data over DMA triggered by HW, but as mentioned before I need to constantly (or after each SCI DMA RX) trigger a dummy dma request so that future SCI DMA RX requests can be triggered.

The dummy transfer should only be needed on the very first DMA transfer to kick start the process. It shouldn't be needed for subsequent DMA transfers. Also, i would consider switching to a SW based trigger that can be triggered within you RX interrupt for the first byte in a packet. This is especically true if you are dealing with fixed packet lengths. You still get the one RX interrupt per packet but the DMA takes care of moving the data around. You would re-enablethe receive interrupt in the completion interrupt for the DMA block transfer complete.

Julio Cesar Aguilar Zerpa said:

I don't know which function does the actual triggering. I've even used the whole code in a loop and nothing. I just get the first transfer.

If you are using HW triggering, it should be triggered by the SCI module as it would instantiate the DMA request every time a byte is received.

Julio Cesar Aguilar Zerpa said:

Btw, I didn't understand what you said about doing a transfer in loopback mode as initialization and that should trigger my dma_sci_rx request.

My intention was to say you initiate a dummy transfer during initialization to take care ot the kickoff of the DMA. If you base it on the RX receive interrupt and a SW trigger, you may be able to avoid this.

Hi there Chuck,

I was able to send and receive periodically with DMA & in digital loop back mode (like it is in the example). I just needed to enable the channels again by calling:

dmaSetChEnable(DMA_CH1, DMA_HW);

dmaSetChEnable(DMA_CH2, DMA_HW);

I then tried to receive data from the sensor but the dma interrupt wasn't even triggered in the first iteration, so I went back to the example and tried to test it in analog loop back mode. I also connected the SCI4 RX and TX pins (NHET117 & NHET119, are they right?). And again nothing is received. I get the DMA TX interrupt, so what am I missing? Digital loop back works but analog doesn't.

In this thread, the guy had success trying to do the same thing. I even tried his control packet configuration. But it didn't work. He also sends the first byte via 'sciSend', which I don't understand why, but I also tried it anyway. And it didn't work.

I also tried your software trigger idea but again without success (the DMA RX interrupt is not called).

/* Addresses of SCI 8-bit TX/RX data */
#define SCI3_TX_ADDR ((uint32_t)(&(sciREG3->TD)))
#define SCI3_RX_ADDR ((uint32_t)(&(sciREG3->RD)))
#define SCI4_TX_ADDR ((uint32_t)(&(sciREG4->TD)))
#define SCI4_RX_ADDR ((uint32_t)(&(sciREG4->RD)))

/* DMA request lines */
#define DMA_SCI3_TX  DMA_REQ31
#define DMA_SCI3_RX  DMA_REQ30
#define DMA_SCI4_TX  DMA_REQ43
#define DMA_SCI4_RX  DMA_REQ42

/* SCI flag operations */
#define SCI_SET_TX_DMA      (1<<16)
#define SCI_SET_RX_DMA      (1<<17)
#define SCI_SET_RX_DMA_ALL  (1<<18)

void dmaConfigCtrlPacket(g_dmaCTRL* ctrl_pkt, uint32 src_addr, uint32 dest_addr, uint32 data_size,
		                 uint32 port_assign, uint32 mode_read, uint32 mode_write, uint32 frame_dest_offset)
{
	ctrl_pkt->SADD      = src_addr;		  		/* source address             */
	ctrl_pkt->DADD      = dest_addr;	  		/* destination  address       */
	ctrl_pkt->CHCTRL    = 0;              		/* channel control            */
	ctrl_pkt->FRCNT	    = data_size;			/* frame count                */
	ctrl_pkt->ELCNT     = 1;              		/* element count              */
	ctrl_pkt->ELDOFFSET = 0;              		/* element destination offset */
	ctrl_pkt->ELSOFFSET = 0;		      		/* element source offset      */
	ctrl_pkt->FRDOFFSET = frame_dest_offset;	/* frame destination offset   */
	ctrl_pkt->FRSOFFSET = 0;              		/* frame source offset        */
	ctrl_pkt->PORTASGN  = port_assign;    		/* port b                     */
	ctrl_pkt->RDSIZE    = ACCESS_8_BIT;	  		/* read size                  */
	ctrl_pkt->WRSIZE    = ACCESS_8_BIT;	  		/* write size                 */
//	ctrl_pkt->TTYPE     = BLOCK_TRANSFER; 		/* transfer type              */
	ctrl_pkt->TTYPE     = FRAME_TRANSFER; 		/* transfer type              */
	ctrl_pkt->ADDMODERD = mode_read;      		/* address mode read          */
	ctrl_pkt->ADDMODEWR = mode_write;     		/* address mode write         */
	ctrl_pkt->AUTOINIT  = AUTOINIT_OFF;   		/* autoinit                   */
}

void prepareDummyDMARequest(g_dmaCTRL* ctrl_pkt_1, g_dmaCTRL* ctrl_pkt_2)
{
	/* Enable SCI 4 as loopback */
	if (ctrl_pkt_2 != NULL)
	{
		sciEnableLoopback(sciREG4, Analog_Lbk);
//		sciEnableLoopback(sciREG4, Digital_Lbk);
	}

//	while (((sciREG4->FLR & SCI_TX_INT) == 0U) || ((sciREG4->FLR & 0x4) == 0x4))
//    {
//	} /* Wait */

	/*Assign DMA request SCI4 transmit to Channel 1*/
	dmaReqAssign(DMA_CH1, DMA_SCI4_TX);

//	/*Assign DMA request SCI4 receive to Channel 2*/
	if (ctrl_pkt_2 != NULL)
	{
		dmaReqAssign(DMA_CH2, DMA_SCI4_RX);
	}

	/* configure dma control packets */
	dmaConfigCtrlPacket(ctrl_pkt_1, (uint32)(&DMA_DUMMY_TX), SCI4_TX_ADDR, dummy_size, PORTA_READ_PORTB_WRITE, ADDR_INC1, ADDR_FIXED, 0);
	if (ctrl_pkt_2 != NULL)
	{
		dmaConfigCtrlPacket(ctrl_pkt_2, SCI4_RX_ADDR, (uint32)(&DMA_DUMMY_RX), dummy_size, PORTB_READ_PORTA_WRITE, ADDR_FIXED, ADDR_INC1, 0);
	}

//	/*Set control packet for channel 1 and 2*/
	dmaSetCtrlPacket(DMA_CH1, *ctrl_pkt_1);
	if (ctrl_pkt_2 != NULL)
	{
		dmaSetCtrlPacket(DMA_CH2, *ctrl_pkt_2);
	}

	/* enable interrupt after RX request is completed */
	if (ctrl_pkt_2 != NULL)
	{
		dmaEnableInterrupt(DMA_CH2, BTC, DMA_INTA);
	}
	else
	{
		dmaEnableInterrupt(DMA_CH1, BTC, DMA_INTA);
	}
}

void startDummyDMARequest(g_dmaCTRL* ctrl_pkt_1, g_dmaCTRL* ctrl_pkt_2)
{
    /* Reset the Flag to not Done*/
    DMA_Comp_Flag = DMA_DUMMY_FLAG;
	memset(DMA_DUMMY_RX, 0, dummy_size * sizeof(uint8));

	/*Set dma channel 0 and 1 to trigger on hardware request*/
	dmaSetChEnable(DMA_CH1, DMA_HW);

	if (ctrl_pkt_2 != NULL)
	{
		dmaSetChEnable(DMA_CH2, DMA_HW);
	}

	/*Enable SCI4 Transmit and Receive DMA Request*/
	sciREG4->SETINT = SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
}

void Update_DMA_Comp_Flag()
{
    /* Set the Flag to Done*/
//	DMA_Comp_Flag = 0x55AAD09E;
	DMA_Comp_Flag = ~DMA_Comp_Flag;

	/* Disable RX DMA Interrupt */
	sciREG3->CLEARINT = SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;

	/* Disable TX & RX DMA Interrupt */
	sciREG4->CLEARINT = SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
}

#pragma WEAK(dmaGroupANotification)
void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (8) */
	if (channel == 0)
	{
		channel0_interrupted = TRUE;
		sci_printf("dma channel 0 interrupted \r \n");
	}
	else if (channel == 1)
	{
		channel1_interrupted = TRUE;
		sci_printf("dma channel 1 interrupted \r \n");
	}
	else if (channel == 2)
	{
		channel2_interrupted = TRUE;
		sci_printf("dma channel 2 interrupted \r \n");
	}

	Update_DMA_Comp_Flag();
/* USER CODE END */
}

Just as info :-)

Best Regards,

Julio

Hi Chuck,

When I created a new project to test this, I forgot to activate the pinmux of the serial interface. This and probably that I had the SCI RX interrupt active were the problem. I am now getting sensor data :-)

Thanks and Regards,
Julio

Hello Julio,

Has the issue been solved?