TMDXRM57LHDK: Receiving data on SCI3 using DMA

dmaSetChEnable(DMA_CH1, DMA_HW);

dmaSetChEnable(DMA_CH2, DMA_HW);

/* Addresses of SCI 8-bit TX/RX data */
#define SCI3_TX_ADDR ((uint32_t)(&(sciREG3->TD)))
#define SCI3_RX_ADDR ((uint32_t)(&(sciREG3->RD)))
#define SCI4_TX_ADDR ((uint32_t)(&(sciREG4->TD)))
#define SCI4_RX_ADDR ((uint32_t)(&(sciREG4->RD)))

/* DMA request lines */
#define DMA_SCI3_TX  DMA_REQ31
#define DMA_SCI3_RX  DMA_REQ30
#define DMA_SCI4_TX  DMA_REQ43
#define DMA_SCI4_RX  DMA_REQ42

/* SCI flag operations */
#define SCI_SET_TX_DMA      (1<<16)
#define SCI_SET_RX_DMA      (1<<17)
#define SCI_SET_RX_DMA_ALL  (1<<18)

void dmaConfigCtrlPacket(g_dmaCTRL* ctrl_pkt, uint32 src_addr, uint32 dest_addr, uint32 data_size,
		                 uint32 port_assign, uint32 mode_read, uint32 mode_write, uint32 frame_dest_offset)
{
	ctrl_pkt->SADD      = src_addr;		  		/* source address             */
	ctrl_pkt->DADD      = dest_addr;	  		/* destination  address       */
	ctrl_pkt->CHCTRL    = 0;              		/* channel control            */
	ctrl_pkt->FRCNT	    = data_size;			/* frame count                */
	ctrl_pkt->ELCNT     = 1;              		/* element count              */
	ctrl_pkt->ELDOFFSET = 0;              		/* element destination offset */
	ctrl_pkt->ELSOFFSET = 0;		      		/* element source offset      */
	ctrl_pkt->FRDOFFSET = frame_dest_offset;	/* frame destination offset   */
	ctrl_pkt->FRSOFFSET = 0;              		/* frame source offset        */
	ctrl_pkt->PORTASGN  = port_assign;    		/* port b                     */
	ctrl_pkt->RDSIZE    = ACCESS_8_BIT;	  		/* read size                  */
	ctrl_pkt->WRSIZE    = ACCESS_8_BIT;	  		/* write size                 */
//	ctrl_pkt->TTYPE     = BLOCK_TRANSFER; 		/* transfer type              */
	ctrl_pkt->TTYPE     = FRAME_TRANSFER; 		/* transfer type              */
	ctrl_pkt->ADDMODERD = mode_read;      		/* address mode read          */
	ctrl_pkt->ADDMODEWR = mode_write;     		/* address mode write         */
	ctrl_pkt->AUTOINIT  = AUTOINIT_OFF;   		/* autoinit                   */
}

void prepareDummyDMARequest(g_dmaCTRL* ctrl_pkt_1, g_dmaCTRL* ctrl_pkt_2)
{
	/* Enable SCI 4 as loopback */
	if (ctrl_pkt_2 != NULL)
	{
		sciEnableLoopback(sciREG4, Analog_Lbk);
//		sciEnableLoopback(sciREG4, Digital_Lbk);
	}

//	while (((sciREG4->FLR & SCI_TX_INT) == 0U) || ((sciREG4->FLR & 0x4) == 0x4))
//    {
//	} /* Wait */

	/*Assign DMA request SCI4 transmit to Channel 1*/
	dmaReqAssign(DMA_CH1, DMA_SCI4_TX);

//	/*Assign DMA request SCI4 receive to Channel 2*/
	if (ctrl_pkt_2 != NULL)
	{
		dmaReqAssign(DMA_CH2, DMA_SCI4_RX);
	}

	/* configure dma control packets */
	dmaConfigCtrlPacket(ctrl_pkt_1, (uint32)(&DMA_DUMMY_TX), SCI4_TX_ADDR, dummy_size, PORTA_READ_PORTB_WRITE, ADDR_INC1, ADDR_FIXED, 0);
	if (ctrl_pkt_2 != NULL)
	{
		dmaConfigCtrlPacket(ctrl_pkt_2, SCI4_RX_ADDR, (uint32)(&DMA_DUMMY_RX), dummy_size, PORTB_READ_PORTA_WRITE, ADDR_FIXED, ADDR_INC1, 0);
	}

//	/*Set control packet for channel 1 and 2*/
	dmaSetCtrlPacket(DMA_CH1, *ctrl_pkt_1);
	if (ctrl_pkt_2 != NULL)
	{
		dmaSetCtrlPacket(DMA_CH2, *ctrl_pkt_2);
	}

	/* enable interrupt after RX request is completed */
	if (ctrl_pkt_2 != NULL)
	{
		dmaEnableInterrupt(DMA_CH2, BTC, DMA_INTA);
	}
	else
	{
		dmaEnableInterrupt(DMA_CH1, BTC, DMA_INTA);
	}
}

void startDummyDMARequest(g_dmaCTRL* ctrl_pkt_1, g_dmaCTRL* ctrl_pkt_2)
{
    /* Reset the Flag to not Done*/
    DMA_Comp_Flag = DMA_DUMMY_FLAG;
	memset(DMA_DUMMY_RX, 0, dummy_size * sizeof(uint8));

	/*Set dma channel 0 and 1 to trigger on hardware request*/
	dmaSetChEnable(DMA_CH1, DMA_HW);

	if (ctrl_pkt_2 != NULL)
	{
		dmaSetChEnable(DMA_CH2, DMA_HW);
	}

	/*Enable SCI4 Transmit and Receive DMA Request*/
	sciREG4->SETINT = SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
}

void Update_DMA_Comp_Flag()
{
    /* Set the Flag to Done*/
//	DMA_Comp_Flag = 0x55AAD09E;
	DMA_Comp_Flag = ~DMA_Comp_Flag;

	/* Disable RX DMA Interrupt */
	sciREG3->CLEARINT = SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;

	/* Disable TX & RX DMA Interrupt */
	sciREG4->CLEARINT = SCI_SET_TX_DMA | SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
}

#pragma WEAK(dmaGroupANotification)
void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (8) */
	if (channel == 0)
	{
		channel0_interrupted = TRUE;
		sci_printf("dma channel 0 interrupted \r \n");
	}
	else if (channel == 1)
	{
		channel1_interrupted = TRUE;
		sci_printf("dma channel 1 interrupted \r \n");
	}
	else if (channel == 2)
	{
		channel2_interrupted = TRUE;
		sci_printf("dma channel 2 interrupted \r \n");
	}

	Update_DMA_Comp_Flag();
/* USER CODE END */
}