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Compiler/TMDXRM57LHDK: SDRAM EMIF DMA access

Marcel Ballmann
Intellectual 460 points

Part Number: TMDXRM57LHDK

Tool/software: TI C/C++ Compiler

Hi,

I'm using the RM57L Hardware Developement Kit. I try DMA write to the SDRAM 16Bit interface I'm but when I use my code I see no tranfer of data also no traffic on the address lines only the WEn is toggling(using a Digitalanalyzer). Using this in main:

emif_SDRAMInit();
/* - creating a data chunk in system ram to start with ... */
loadDataPattern(D_SIZE, &TXDATA_RAM[0], 0xFFFFFFFF ); // 0x5A5A5A5A

/* - configuring dma control packets */
g_dmaCTRLPKT1.SADD = (uint32)TXDATA_RAM; /* source address */
g_dmaCTRLPKT1.DADD = (uint32)(0x80000000); //(0x08078000); /* destination address; SDRAM */
g_dmaCTRLPKT1.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT1.FRCNT = F_COUNT; /* frame count */
g_dmaCTRLPKT1.ELCNT = E_COUNT; /* element count */
g_dmaCTRLPKT1.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.PORTASGN = PORTA_READ_PORTA_WRITE;
g_dmaCTRLPKT1.RDSIZE = ACCESS_32_BIT; /* read size */
g_dmaCTRLPKT1.WRSIZE = ACCESS_32_BIT; /* write size */
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT1.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_OFF; /* autoinit */


g_dmaCTRLPKT2.SADD = (uint32)(0x80001000); //(0x80001000)(0x08076000); /* source address */
g_dmaCTRLPKT2.DADD = (uint32)RXDATA_RAM; /* destination address */
g_dmaCTRLPKT2.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT2.FRCNT = F_COUNT; /* frame count */
g_dmaCTRLPKT2.ELCNT = E_COUNT; /* element count */
g_dmaCTRLPKT2.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT2.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT2.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT2.PORTASGN = PORTA_READ_PORTA_WRITE;
g_dmaCTRLPKT2.RDSIZE = ACCESS_32_BIT; /* read size */
g_dmaCTRLPKT2.WRSIZE = ACCESS_32_BIT; /* write size */
g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT2.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_OFF; /* autoinit */

/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT1); //tx
//dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT2); //rx

/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH1, DMA_SW);
//dmaSetChEnable(DMA_CH0, DMA_SW);

/* Enable Block Transfer Complete interrupt for the receive after transfer complete */
//dmaEnableInterrupt(DMA_CH0, BTC, DMA_INTA);


dmaEnable();

In the sys_link I use this address

VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0007BB00
SHAREDRAM (RW) : origin=0x0807D000 length=0x00003000

/* USER CODE BEGIN (3) */
SDRAM (RWX) : origin=0x80000000 length=0200000000

Thank you

Marcel

  • 0
    TI__Mastermind 49120 points

    Hi Marcel,

    It appears to be an issue with initialization of the EMIF. Can you please include the emif_SDRAMInit() function as well as the configuration of the I/O multiplexing?

    Regards,
    Sunil

  • 0 in reply to Sunil Oak
    TI__Guru**** 196526 points
    Hello Marcel,

    The Cache is enabled as default. The MPU setting for SRAM is write-back. If write-back is used, sometimes the up-to-date data is in the cache. Please do a test with write-through or with cache disabled.
  • 0 in reply to QJ Wang
    Intellectual 460 points

    Hi QJ,

    I have tried it like this    

    RAM     (RW) : origin=0x08001500 length=0x0007BB00

    SHAREDRAM (RW) : origin=0x0807D000 length=0x00003000

    SDRAM (RW) : origin=0x80000000 length=0200000000

    But it does not Work.

    I also have set the Region for the DMA RAM in write-through.

    As also you can see in the Digital Analyzer only Wn is toggling the Data line and Address lines are low.

  • 0 in reply to QJ Wang
    Intellectual 460 points

    Hi QJ ,

    I'm a little bit further with my investigations. The loadDataPattern routine was wrong. But please I don't understand  RDSIZE and  WRSIZE, FRCNT  and ELCNT how should I config this with my EMIF 16Bit data interface?

    BR

    Marcel 

  • 0 in reply to Marcel Ballmann
    TI__Guru**** 196526 points

    Hello Marcel,

    Your DMA configuration is correct. The only things which blocks data transfer to SDRAM is cache or improper EMIF settings (pinmux, timing).

    1. disable the cache (HALCoGen MPU panel)

    2. use the pinmux and emif config files attached

    3. use main.c enclosed to do write/read test without DMA enabled

    void main(void)

    {

       /* USER CODE BEGIN (3) */

       unsigned short *sdram = (unsigned short *) 0x80000000;

       unsigned short readback[3];

       {

           *(sdram + 0) = (unsigned short) 0xA5A5;

           *(sdram + 1) = (unsigned short) 0xb5b5;

           *(sdram + 2) = (unsigned short) 0xc5c5;

       }

       readback[0] = *(sdram + 0);

       readback[1] = *(sdram + 1);

       readback[2] = *(sdram + 2);

    }

    7120.HL_emif.c5758.HL_pinmux.c