TM4C123GH6PM: Bit-banding. Why are alias words 4 apart instead of sequential ??

I believe it is 4 bytes apart, not 4 words. 1 word is 4 bytes in the ARM architecture, so the 4-byte spacing makes some sense. I've not used bit-banding yet, and I agree that some of the data sheets are a little confusing on this feature.

Keith Scott said:

Is it just something in the design of the hardware and we really don’t need to care, or is there some logical reason that I can’t see

The About bit-banding section of the  ARM® Cortex®‑M4 Processor Technical Reference Manual says:

Bit-banding enables every individual bit in the bit-banding region to be directly accessible from a word-aligned address using a single LDR instruction.

i.e. it was the design intention for the bit-band aliases to be spaced 4 apart to use word-aligned addresses.

The Address alignment section of the Cortex-M4 Devices Generic User Guide explains the benefit of using aligned addresses:

Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned.

Thanks guys.

Chester,
I'll check out those links for further reading.
OK, so for whatever technical reasons, let's just say there are hardware benefits that result in speed, etc. That will pacify my curiosity for now.

Brian,
I was trying to figure that out too (4 bytes or 4 words apart). However, the memory map I assumed to be made up of 32 bit words. After all, this is a 32 bit processor.
So in my opening example, where there is bit-band alias address 0x22000000 (representing bit[0]) and 0x22000004 (representing bit[1]), I took it they were 4 WORDS apart.

Could anyone confirm or correct that assumption.

Hi Keith,
The ARM architecture is only byte addressable, not bit addressable. If the ARM architecture is bit addressable then you would not need the bit-banging using the alias address at all. You can just write to the bit address with the value. With the alias address by means of mapping each bit to a 32-bit address, it greatly eases the hardware address decoding. The lower 2 address bits will be simply ignored. The hardware decoder just looks at the rest of offset address bits to know which bit position is to access. For example, if you want to write to only bit 2 the alias address is 0x22000008. If you ignore the last 2 address bits the 0x8 becomes 0x2 which means to access bit 2.

Thanks again Chester & Charles.

It all makes perfect sense now that I know the address space is byte addressable. Sorry for my present lack of knowledge, I am regularly reading literature on this micro but am still right at the beginning relatively speaking. Quite a bit more to study than an AVR data sheet LOL.

Keith.

I downloaded that manual and checked out the section you mentioned. For others reference and understanding, here's part of the explanation from the manual:

The ARMv7-M architecture uses a single, flat address space of 2(to power 32) 8-bit bytes.
Byte addresses are treated as unsigned numbers, running from 0 to 2(to power 32) - 1.
This address space is regarded as consisting of 2(to power 30) 32-bit words, each of whose addresses is word-aligned, meaning that the address is divisible by 4.
The word whose word-aligned address is A consists of the four bytes with addresses A, A+1, A+2, and A+3.
The address space can also be considered as consisting of 2(to power 31) 16-bit halfwords, each of whose addresses is halfword-aligned, meaning that the address is divisible by 2.
The halfword whose halfword-aligned address is A consists of the two bytes with addresses A and A+1.

It all makes sense now. I would never have guessed a 32 bit micro used a byte divisible address space. So effectively each 32 bit WORD address space is 4 apart; 0, 4, 8, 12, etc (bytes that are word aligned).

Keith.

Hi Keith,

Keith Scott said:

So effectively each 32 bit WORD address space is 4 apart; 0, 4, 8, 12, etc (bytes that are word aligned).

  Just a small correction on "(bytes that are word aligned)", the individual bytes are still byte (8-bit) aligned. For example, you can write to a byte address (i.e. 0x1001 or 0x1002) using a STRB instruction.  The byte addresses are not word aligned. But you meant to say that 4 bytes making up a word is word aligned then you are correct. 

  Don't want to complicate things further, the Cortex-M architecture also supports unaligned access which means you can possibly do a STR (a 32-bit write) to an address that is not word aligned. The CPU simply breaks up an unaligned access into multiple aligned accesses. However, unaligned access in the bit-band region will produce unpredictable behavior. Disregard the last paragraph if you wish as it is not directly related to your original question. :-)

Charles Tsai said:

The ARM architecture is only byte addressable, not bit addressable. If the ARM architecture is bit addressable then you would not need the bit-banging using the alias address at all.

Another small correction - this feature is called bit-banding, not bit-banging.

Bit banging is something totally different, and is done without hardware support or acceleration, at least usually.

Thanks Charles,

yes I was meaning the latter of your first paragraph.

I just had a thought about maybe why a 32 bit micro has a byte addressable memory space. ASCII characters, serial transmission, and no doubt plenty else will use bytes, so if you could only address a 32 bit word it would be wasteful of memory storing a byte in a word space, or it would take a lot more code to mask 4 bytes in a 32 bit word.

That was just a guess.

Keith

Thanks for catching the typos, I meant bit-banding, not bit-banging. :-)

Few here were not (even) a "bit" concerned...