TMS570LC4357: STC Self Test

Hi Rabie,

I've forwarded your post to one of our SW leads to see if they may be able to help. You should hear back from them shortly.

Hi,

Can you please send us the complete startup file so that we can have a look at how the init part is done?

Thanks and Regards,

Veena

Hi,

Ok. Actually i tried to start two Self Test functions, but both of them failed to start and returning false.
1) SL_SelfTest_PBIST(). 2) SL_SelfTest_STC().

Down below you will find my code i am trying to debug on the TMS570LC4357.

Thanks and Regards
/************************************************/
/** @file HL_sys_startup.c
* @brief Startup Source File
* @date 05-Oct-2016
* @version 04.06.00
*
* This file contains:
* - Include Files
* - Type Definitions
* - External Functions
* - VIM RAM Setup
* - Startup Routine
* .
* which are relevant for the Startup.
*/

/* USER CODE BEGIN (0) */
/* USER CODE END */


/* Include Files */

#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_sys_vim.h"
#include "HL_sys_core.h"
#include "HL_esm.h"
#include "HL_sys_mpu.h"
#include "HL_reg_stc.h"

/* USER CODE BEGIN (1) */
#include "../../TILibs/SafeTIDiag/2.3.1/safety_library/include/sl_types.h"

/* USER CODE END */

/* USER CODE BEGIN (2) */
#define STC_ENABLE 1U
#define PBIST_ROM_ENABLE 1U

/* USER CODE END */

/* External Functions */

/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
extern int main(void);
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(int _status);

/* USER CODE BEGIN (3) */
/**************************** external functions ****************************/
extern boolean SL_SelfTest_STC(register SL_SelfTestType testType, register boolean bMode, register SL_STC_Config* config);
extern boolean SL_SelfTest_PBIST (register SL_SelfTestType testType, register uint64 ramGroup, register uint32 algoInfo);
extern boolean SL_SelfTest_Status_PBIST(SL_PBIST_FailInfo* param1);
extern boolean SL_SelfTest_PBIST_StopExec(void);
extern void errata_PBIST_4(void);
/****************************************************************************/
/* USER CODE END */

/* Startup Routine */
void _c_int00(void);
/* USER CODE BEGIN (4) */
/* USER CODE END */

#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)

void _c_int00(void)
{

/* USER CODE BEGIN (5) */
/* USER CODE END */

/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();

/* Initialize Stack Pointers */
_coreInitStackPointer_();

/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
switch(getResetSource())
{
case POWERON_RESET:
case DEBUG_RESET:
case EXT_RESET:

/* USER CODE BEGIN (6) */
case NO_RESET:
/* USER CODE END */

/* Initialize L2RAM to avoid ECC errors right after power on */
_memInit_();

/* USER CODE BEGIN (7) */
/* USER CODE END */

/* USER CODE BEGIN (8) */
/* USER CODE END */


/* USER CODE BEGIN (9) */
/* USER CODE END */

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

/* USER CODE BEGIN (10) */
/* USER CODE END */

/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}

/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();

/* USER CODE BEGIN (11) */
_enable_interrupt_();

#if PBIST_ROM_ENABLE == 1U
/*The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM*/
errata_PBIST_4();

{
boolean retVal;
SL_PBIST_FailInfo pbistStatus;

/* Start PBIST on STC and PBIST ROM*/
retVal = SL_SelfTest_PBIST(PBIST_EXECUTE,
PBIST_RAMGROUP_01_PBIST_ROM |
PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
PBIST_RAMGROUP_04_STC2_ROM_NHET,
PBISTALGO_TRIPLE_READ_FAST_READ |
PBISTALGO_TRIPLE_READ_SLOW_READ);
if(retVal == false)
{
/*Fail to start PBIST*/
while(1);
}

/* Wait for PBIST on ROM to complete */
while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
SL_SelfTest_PBIST_StopExec();

if(pbistStatus.stResult != ST_PASS)
{
/* PBIST fail*/
while(1);
}

/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif
/* USER CODE END */

/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();

/* Initialize VIM table */
vimInit();

/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();

/* USER CODE BEGIN (13) */
/* Start CPU Self-Test */
#if STC_ENABLE == 1U
{
volatile boolean retVal;
SL_STC_Config stcSelfTestConfig;

stcSelfTestConfig.stcClockDiv = 2;
stcSelfTestConfig.intervalCount = 1;
stcSelfTestConfig.restartInterval0 = TRUE;
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF;

retVal=SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);

if(!retVal)
{
/*Fail to start STC Self-Test */
while(1);
}
}
#endif
/* USER CODE END */

break;

case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
break;

case WATCHDOG_RESET:
case WATCHDOG2_RESET:
/* USER CODE BEGIN (15) */
/* USER CODE END */
break;

case CPU0_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */

/* USER CODE BEGIN (17) */
/* USER CODE END */

/* USER CODE BEGIN (18) */
/* USER CODE END */

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

/* USER CODE BEGIN (19) */
#if STC_ENABLE == 1U

if ((stcREG1->STCSCSCR & 0xFU) == 0xAU)
{
/* check if the self-test fail bit is set */
if ((stcREG1->STCGSTAT & 0x3U) != 0x3U)
{
/* STC self-check has failed */
while(1);
}
/* STC self-check has passed */
else
{
/* clear self-check mode */
stcREG1->STCSCSCR = 0x05U;
/* clear STC global status flags */
stcREG1->STCGSTAT = 0x3U;
/* clear ESM group1 channel 27 status flag */
esmREG->SR1[0U] = 0x08000000U;
{
SL_STC_Config stcSelfTestConfig;
stcSelfTestConfig.stcClockDiv = 0; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
SL_SelfTest_STC(STC1_RUN, TRUE, &stcSelfTestConfig);
while(1); /* STC failed to start */
}
}
}
/* CPU reset caused by CPU self-test completion */
else if ((stcREG1->STCGSTAT & 0x1U) == 0x1U)
{
/* Self-Test Fail flag is set */
if ((stcREG1->STCGSTAT & 0x2U) == 0x2U)
{
/* Call CPU self-test failure handler */
while(1);
}
/* CPU self-test completed successfully */
else
{
/* clear STC global status flag */
stcREG1->STCGSTAT = 0x1U;
/* Continue start-up sequence after CPU STC completed */
}
}
/* CPU reset caused by software writing to CPU RESET bit */
else
{
/* Add custom routine here to handle the case where software causes CPU reset */
}


#endif
/* USER CODE END */
break;

case SW_RESET:
/* USER CODE BEGIN (20) */
/* USER CODE END */
break;

default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
break;
}

/* USER CODE BEGIN (22) */
/* USER CODE END */

_mpuInit_();

/* USER CODE BEGIN (23) */
/* USER CODE END */

_cacheEnable_();

/* USER CODE BEGIN (24) */
/* USER CODE END */


/* USER CODE BEGIN (25) */
/* USER CODE END */

/* initialize global variable and constructors */
__TI_auto_init();
/* USER CODE BEGIN (26) */
/* USER CODE END */

/* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
exit(0);


/* USER CODE BEGIN (28) */
/* USER CODE END */

}

/* USER CODE BEGIN (29) */
/* USER CODE END */



/* USER CODE BEGIN (30) */
/* USER CODE END */
/*********************************/

Hi Rabie,

SL_SelfTest_STC will never return a status. The function starts the STC selftest and causes a CPU reset after the test. The status can be checked as part of CPU reset handler.
Although the function prototype says it returns the status, it is a non-returning function. It is also not recommended to do single stepping inside the function.
There is a sample startup file available as part of HALCoGen which shows how to run selftests using SafeTI Diagnostics Library. There you can find the actual status check for STC tests is done as part of CPU_RESET case.

Thanks and Regards,
Veena

Hi Veena,

thanks for your Answer, but i disagree with you about this issue. The two functions i am talking about <SL_SelfTest_PBIST()> and <SL_SelfTest_STC()> are from type boolean, so they return something (TRUE or FALSE). Each time i call them in my code, they return false, which means intuitively, they fail to start.
By the way the sample code i am using, is from the HALCoGen Help topics, which checks the return value of the self test function and goes into the while(1) loop, if the return value is false.

So my question again why the self test functions are returning false? and how to ensure that they are working?
I used exactly the sample code explained in the HALCoGen, but this is not working. Please support me with a sample code how to run the self test using the SafeTI Diagnostics Library for TMS570LC4357.

Thank you and Regards.

Hi Rabie,

SL_SelfTest_PBIST is a function which returns a TRUE/FALSE status. I will look into the issue why it is returning FALSE and get back to you.
The function SL_SelfTest_STC, eventhough it is a TRUE/FALSE returning function, if it executed in the desired manner, it should never return. It executes the CPU STC test and immediately generates a CPU reset. The status of the test needs to be checked in the CPU reset handler.
If the function SL_SelfTest_STC eturns to the next statement, it means the test was not triggered properly. I will look into this issue as well.

Thanks and Regards,
Veena

Hi,

I was unable to recreate the scenario. I replaced my startup file with the file you had sent and the PBIST and STC tests seems to execute without any issues.

STC self test function created a CPU reset and did not return to the next statement where the retVal was checked.

retVal=SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);

if(!retVal)
{

/*Fail to start STC Self-Test */
while(1);

}

Both the tests may return fail when the ESM error is set. It does not proceed to the test if the ESM error pin set. Please check whether the ESM error status is set or not before executing the tests.

Thanks and Regards,

Veena

Hi Veena,

it is really a good news to hear that, the code sample i sent it to you, is working.

But unfortunately i still have the same problem while executing the STC self check.

My first question is:

Which Register did you mean when saying "ESM error/ESM error pin/ESM error status"?

i did the following before calling "SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig)" :

#if STC_ENABLE == 1
{
boolean retVal;
SL_STC_Config stcSelfTestConfig;

esmClearStatus(esmGROUP1,esmCHANNEL52);

esmActivateNormalOperation();

esmREG->EEPAPR1 = 0x00000000;

stcSelfTestConfig.stcClockDiv = 2;                                        /* STC Clock divider = 1 */

stcSelfTestConfig.intervalCount = 1;                                    /* One interval only */

stcSelfTestConfig.restartInterval0 = TRUE;                        /* Start from interval 0 */

stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF;          /* Timeout counter*/

retVal=SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);

if(!retVal)

{

while(1); /* STC failed to start */

}

}

#endif

I looked at the registers which may be important for my case and i found the following:

before calling SL_SelfTest_STC(), the Register ErrPinStat = 0x00000001 and ErrKey=0x00000000

after calling SL_SelfTest_STC(), the Register Stc1_GStat = 0x00000A03 and Stc1_FStat=0x00000003

The function SL_SelfTest_STC() didn't return anything, that is right , but it is not reset the CPU, no matter how long i wait.

Could you tell me please exactly which registers should i set, before calling the STC self test and how long did i takes time to reset the CPU?

Thank you and best regards

Rabie

 

Hi Rabie,

I was referring to the ESM error pin status. The value is reflected in the register ErrPinStat. The register value should be 1 before running the STC selftest. Looks like the there was no ESM error in your case.

If the selftest neither returned and nor did it generate a CPU reset,  where did the code execution go? How did you check that the CPU reset never occurred?

How I check this is, I keep a loop-to-itself instruction in the CPU reset handler.

Once the PC hits the instruction  "B $", it does not proceed to the next statement unless you force the PC to move to the next statement. This way, I know CPU reset has occurred.

Thanks and Regards,

Veena

Hi Veena,

thank you for the answer. 

in the last 2 days it was successful to kickoff the function SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig) and to verify that this function generates a CPU reset by looking at the Debug Window left above. 

But now my very big Problem is that the register "ErrPinStat" is always Zero, which means an error has been occurred. I did many things to clear this register by writing "ErrPinStat = 0x01", but this is not working and didn't change the value of the register. I then used all possible functions in the "ESM" module, but still not working. I also tried to reduce the value of the "LtCnt" register and to write "ErrKey = 0x5", but also this has no effect.

As you know the Self Tests functions will never kicked off if the "ErrPinStat" is equal to Zero. So How could i reset this register "ErrPinStat" back to '1' ?

And How to know which reason behind this value inside the register?

Thanks for helping

Regards 

Rabie

 

Hello Rabie,

Can you have a look at the ESM status registers to identify which ESM channel has been flagged? You can access these registers in the register browser in CCS.

Hi Chuck,

in the following diagram you can see the registers. The "ErrPinStat" is always Zero which make impossible to kickoff a Self Test function. According to the Document (spnz180d) Device#56, this is a known issue. I tried to solve it using the described Workaround, but this is not working. I also run the Program without using the JTAG, but this is also not working. 

Thank you and Regards

Hello Rabie,

I see in the list above that ErrorKey = 0x00000005. Can you try writing as 0? Writing as 0 should return the nERROR pin behavior to normal mode and deassert it.