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Hi Champs,
According to datasheet table 24-35, there is Tsft timing which mean I2CSCL/I2CSDA fall time. The max number is 10ns. Could you please tell me does this SPEC apply on master mode? If TM4C123GH6ZRB is slave , clock should be determined by master. Should master clock followed 10ns SPEC as well ? thanks!
Might the "champs" at Phillips - who devised the I2C spec - prove a better destination for such question?
You appear to be asking about the "Tsft" requirement - forced upon an I2C Master (likely NOT another TM4C) - and that spec should fall w/in Phillips defining I2C document...
That fall time is dependent upon the value of the (required) I2C pull-up resistor - and capacitive loading as well - is it not? It is suspected that there IS "wiggle room" as the spec was created long ago - when rise/fall times well exceeded those obtained more recently...
Bob Crosby said:The actual timing requirements for the I2C bus depend on the mode (bus speed). There is some more information in this application note:
www.ti.com/.../slva695.pdf
When firms adopt the brand/trade or "recognized standard" of another (via use of I2C, here) - the specifications of the "Controlling Authority - which was Phillips" - are those which demand compliance.
It is reasonable to consider that the "I2C Master" may be from (other) than this vendor - thus referral to "this vendor's I2C spec" (if that's what the referenced doc truly is) - provides an "indirection" - and introduces a potential for error and/or uncertainty. Can that be good - should it "replace" the earlier (broader & more reflective advice)?
The advice to seek "some other spec" - which may not properly reflect the intent of the "standard's originator/owner" - places the user in (some) jeopardy... (i.e. "your advice" - conflicting w/that offered (more properly) here - earlier)
cb1_mobile said:Might the "champs" at Phillips
Presumably NXP now. I doubt anyone at Philips (one l only) has much definitive anymore.
Robert