Part Number: TM4C123GH6ZRB
Hi Champs,
According to datasheet table 24-35, there is Tsft timing which mean I2CSCL/I2CSDA fall time. The max number is 10ns. Could you please tell me does this SPEC apply on master mode? If TM4C123GH6ZRB is slave , clock should be determined by master. Should master clock followed 10ns SPEC as well ? thanks!