NHET RAM Parity Check when CPU Read but NHET doesn't execute the instruction

Pashan

Hello,

I find the following statement in the TRM for TMS570 within the section [18.4.2.3 Parity Checking]:

"The parity check is performed when the NHET execution unit makes a read access to NHET RAM, but also when a different master (e.g. CPU, HTU, DMA,...) performs the read access."

I am trying to check Parity Error feature while CPU is READing NHET RAM with Parity Error. It doesn't occur. But when NHET READ the same NHET RAM location, Parity Error does occur.

Can anyone tell me, if that is the expected behaviour as it doesn't match the line from the TRM as shown above?

Thank you.

Regards

Pashan

over 15 years ago

0 Hari49672 over 15 years ago

TI__Prodigy 365 points

Hi Pashan,

I have forwarded your query to our expert team members, will get back to you asap

Regards

Hari

0 Anthony F. Seely over 13 years ago in reply to Hari49672

TI__Guru 68830 points

Sorry for this (much) belated answer. Just checked this again w. the NHET designer since we want to clarify the TRM.

Parity is checked when the CPU, HET, and HTU access the NHET/N2HET RAM.

However, if you try reading the RAM just through a window in CCS, the CPU access will be marked as a debug access.

Debug accesses do not trigger a parity check.

0 Pashan None over 13 years ago in reply to Anthony F. Seely

Genius 5660 points

Hello Anthony,

Thank you for the reply at last.

Regards

Pashan

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NHET RAM Parity Check when CPU Read but NHET doesn't execute the instruction