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LAUNCHXL2-570LC43: FreeRTOS, prefetchEntry TMS570lc43

Roman Kosiy
Intellectual 320 points
Part Number: LAUNCHXL2-570LC43

Good day. I have a question.

Im use FreeRTOS for my small project. When i run every task or function that uses freertos api from the main file - everything works fine.
When i try to move tasks or functions to the other file in the other directory and run them, i get prefetchEntry when it goes to xQueueReceive or xEventGroupSetBits and etc (the scheduler starts without any issues, i included header files with the protorypes, and freertos files in the every file with functions). 
What i noticed is that, for example, xQueueReceive does its job (dataObject received, CCS debuger showed that) , but then - prefetchEntry.

So what is the problem? i dont get it. 
What does prefetchEntry exactly mean then? 

Im a bit of Java programmer and errors statckTrace is understandeable, but here... i just dont understand what is this...)

  • 0
    Expert 1995 points
    Prefetch is when the CPU collects a block of op code. If it attempts to collect the instruction from an restricted area, there will be an exception.

    These are symptoms of some often repeated problems.
    1). Your source code does not match the library (calls of functions in the library go to the wrong place).
    2). Your compiler is not creating the instructions in the expected manner (wrong options or you have the wrong library for that compiler).
    3). You have not defined the memory areas to allow access to important code or libraries.

    Prefetch obscures the exact problem, since a block of memory is less descriptive (where exactly is the function call in that block, which number is the address).
  • 0
    TI__Guru 59540 points
    Hello Roman,

    You can also use the CP15 fault status registers to see information about the exception such as which domain it is happening in and what the offending address was that cause it. This often will help determine the root cause. The data and instruction fault status registers are viewable through the registers window in CCS. The bit definitions are defined in the ARM user guide for the Cortex-R5F (search for DFSR and/or IFSR).

    The ARM user guide is available on the ARM website as an online manual or as a downloadable PDF.

    For the downloadable PDF version: infocenter.arm.com/.../DDI0460D_cortex_r5_r1p2_trm.pdf

    For the online version: infocenter.arm.com/.../index.html