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LAUNCHXL2-570LC43: EMIF SDRAM acsess TMS570lc43

Part Number: LAUNCHXL2-570LC43
Other Parts Discussed in Thread: HALCOGEN

I have a structure.

struct TelemPackStruct
{
                 uint32_t tmMarker;
                 float32_t    wx ;
                 float32_t    wy ;
                 float32_t    wz ;
                 float32_t    m1 ;
                 float32_t    m2 ;
                 float32_t    m3 ;
                 float32_t    q0 ;
                 float32_t    q1 ;
                 float32_t    q2 ;
                 float32_t    q3 ;
     struct BinData{
                 uint32_t seconds            :32;
                 uint32_t indication         :8;
                 uint32_t mode               :8;
                 uint32_t modeArea            :8;
     }binDataTM;

};

I need to save this type of structure every second with different values in the emif.

I  enabled the emif in the Halcogen (sdram, async1,2,3, pinmux, driver).

I modified the linker file :

MEMORY
{
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    KERNEL  (RX) : origin=0x00000020 length=0x00008000 
    FLASH0  (RX) : origin=0x00008020 length=0x001F7FE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00000800
    KRAM    (RW) : origin=0x08000800 length=0x00000800
    RAM     (RW) : origin=(0x08000800+0x00000800) length=(0x0007F800 - 0x00000800)

/* USER CODE BEGIN (2) */
 	SDRAM   (RXW) : origin=0x80000000 length=0x007FFFE0
/* USER CODE END */
}

and

SECTIONS
{
    .intvecs : {} > VECTORS
    /* FreeRTOS Kernel in protected region of Flash */
    .kernelTEXT  align(32) : {} > KERNEL
    .cinit       align(32) : {} > KERNEL
    .pinit       align(32) : {} > KERNEL
    /* Rest of code to user mode flash region */
    .text        align(32) : {} > FLASH0 | FLASH1
    .const       align(32) : {} > FLASH0 | FLASH1
    /* FreeRTOS Kernel data in protected region of RAM */
    .kernelBSS    : {} > KRAM
    .kernelHEAP   : {} > RAM
    .bss          : {} > RAM
    .data         : {} > RAM

/* USER CODE BEGIN (4) */
    .telem  : {} > SDRAM
/* USER CODE END */
}

I defined an array of structs

#define NUM_OF_PACKS   1024

struct  TelemPackStruct  telemetry [NUM_OF_PACKS] __attribute__((section(".telem")));

The problem i found is the following.

__attribute__((section(".telem"))) volatile  struct  TelemPackStruct  telemetry [NUM_OF_PACKS];

void foo(){
    volatile struct TelemPackStruct tmToRead;
    //filling tmToRead
    telemetry[0]=tmToRead;
 
    //telemetry[0].q1=tmToRead.q1; does the same problem

}

When i try to write telemetry[0] that is stored in the EMIF, it writes only one variable (not single in the structure) and writes it on the WHOLE SDRAM (include ).

  • Hello Roman,

    I tested on my LC43x board, could not produce the problem. What is your EMIF configuration and MPU settings?

  • Wow. Thanks.Its realy settings then, but i dont know where is the problem. Can you send your project?

    My EMIF configuration is equals to the Halcogen's emif example. Dont realy know about MPU config..

    realized that my emif_SDRAMInit() is empty. in the example nothing is said about this. tried emif_SDRAM_StartupInit(), nothing.

    EDIT. MPU region is enabled and its with default settings.

    Noticed a thing. When i define

    SDRAM   (RXW) : origin=0x80000000 length=0x007FFFE0

    it writes nothing to sdram.

    when its

     	SDRAM   (RXW) : origin=0x80000004 length=0x007FFFE0   //or 0x80000002
    

    it causes my problem.

    Checked everything again, regenerated code as it is shown in the emif_example. nothing changed

  • still looking for an answer :)
  • Hello Roman,

    Attached is my working project. I use the same struct "TelemPackStruct" and link cmd.

    5582.TMS570LC4357_SDRAM.zip

  • What helped me here is..

    its the default in halcogen. What i changed when i downloaded your project is the TYPE. DOnt realy know why this is important to change it but.. i changed and it worked.

    Changed to 

  • Hello Roman,

    The ARM TRM describes shared normal memory as "For normal mapped that is shared between several processors." It describes non-shared normal memory as "For normal memory that only a single processor uses."

    In the lockstep architecture configuration, the 2nd core is a checker / diagnostic channel. it does not act independently and its actions only are used to determine if there is an error. The shareable and non-shareable should not affect the test result.

    I tried both settings: shareable and non-shareable, and got the the same result, and could not produce the issue you mentioned.