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Can a TM4C12x boot without ADC VREFA+ ?

Patrick Herborn
Intellectual 520 points
Other Parts Discussed in Thread: REF3233, LM7705

According to the datasheet, VREFA+ must be at least 2.4 volts, and can be up to VDDA. This is easy to ensure - you just link VDDA with VREFA+ even if you are not using an external precision reference.

Also, the datasheet explicitly states that VDD, VDDA and VDDC *MUST* come up in order for the device to boot at all (makes sense).

What is not clear is whether the device can boot with VREFA+ at 0V but with the rest of the part powered ?The datasheet doesn't suggest the part wouldn't boot - just that it would be outside of spec. The question being : what is the consequence of being out of spec ? If it will draw excessive current that would be bad. If it just didn't return sensible ADC readings, that would be fine.

Any insights appreciated,

Pat.

  • 0
    TI__Guru 72500 points
    Hi Pat,
    Just that the part is outside of spec and the ADC will not work.
  • 0 in reply to Bob Crosby
    Guru 117855 points

    Greetings,

    Might several other peripherals suffer as well?    I'm thinking of the MCU's Analog Comparators - in specific - yet I believe there may exist others.

  • 0 in reply to Bob Crosby
    Intellectual 520 points

    Hiya Bob!

    Many thanks for your response clarifying that the device will still boot, but that the ADC won't work - that is fine for the intended application.

    Best regards,

    Pat.

  • 0 in reply to cb1_mobile
    Intellectual 520 points
    Hiya cb1!

    Now that you mention it, I do recall reading that the comparators also use VREFA in some way, many thanks for pointing that out. I am not worried about the ADC or Comparators, so that would still be OK for the application. As long as the Cortex M4F, USB and Flash Memory are operational without VREFA being present, all should be good.

    Best regards,

    Pat.
  • 0 in reply to Patrick Herborn
    Guru 117855 points

    HiYa back, Pat

    I've been at/around this forum over TEN Years - I cannot recall anyone else - posing your "VREF_A+" question.    (says something - does it not?)

    What I found interesting (and still, unexplained) is, "Why one would choose tying VREF_A+ to Gnd. - rather than VDDA?"    (layout ease - or simple "mistake" - are best guess - from my feeble view.)

    Now you're quite clear in, "Not requiring the ADC - and/or Analog Comparator (& possibly a few (unnamed) others)" - yet can you, "Cast that (relaxed) requirement in concrete?"      Forever?    

    Requirements change - new opportunities arise (one hopes) - and my firm's intent is to, "ALWAYS Provide for the "Greatest Functionality" possible!" (w/in reason)       I can report that such "provisioning" has saved us - either an ugly "board hack" - or the unwanted cost, time, effort of a "board spin" - multiple times.

    Please take this guidance into consideration - you're free to "do anything" - yet I've tried to "make the clear case" for, "Expanding your board's capability" - rather than SO limiting it...

  • 0 in reply to cb1_mobile
    Intellectual 520 points

    Hiya cb1!

    Many thanks for your continued interest, thoughts, concerns and suggestions.

    Whilst I didn't feel the need to bore everyone reading the thread by posting the exact reasons for my question (and, as evidenced by Bob's response, this was superfluous), I appreciate your taking the time to contemplate my scenario and I feel it is only fair that I should reciprocate and explain :

    In the specific application, VREFA- and VREFA+ are driven by servo (read: able to sink as well as source current) reference generators - in this case at 150mV and 3150mV (derived from a REF3233 bandgap reference). This accounts for two of four references generated in the same package. One of the other reference generators outputs 5000mV, thereby precluding the use of a 5V rail for this package - it has to be higher (or I need more packages with different supplies).

    You will have noticed I made reference to the Cortex M4F, the USB and the Flash Memory, which alludes to the specific usage scenario I was contemplating - reprogramming the flash memory using the USB.

    Since VDD, VDDA and VDDC are all lower than VBUS, it is possible to power those from VBUS, negating the need to power the board with anything other than the USB lead in this usage scenario. What I cannot do correctly is to power the reference generators. A boost converter from VBUS could raise that and power up the generators. A diode-feed from VBUS to the reference generators' power rail would yield (inaccurate) non-zero voltages, but the simplest, lowest board space (and cost) option overall is to just not power them up. That inevitably leads to the question asked - what happens if power is applied to VDD,VDDA and VDDC, but VREFA+ remains at 0V ?

    We are definitely in agreement in keeping the design as flexible as possible - at the same time I didn't see the point of increasing board complexity unnecessarily - ie if the sole consequence is that the ADC and Comparators will not work, in a usage scenario that does not call for their operation, then the zero board space and component cost of that solution is attractive. If, on the other hand, Bob had stated that they MUST be in spec for the part to work at all, then I would have had to engineer a way to power them up, even when they are not needed per se.

    Best regards,


    Pat.

  • 0 in reply to Patrick Herborn
    Guru 117855 points

    Wow - so much unexpected - AND terrifically detailed.      Perhaps (others) landing here - share my confusion - and desire for clarification.

    You note that "VREFA- & VREFA+" -  "If and when required/used" -  stem from a servo Ref Gen - outputting 0V150 & 3V150.     Yet - at least to me - the uniqueness of that choice is, (pardon) insufficiently explained.

    It would seem quite possible (and easier) to:

    • route your board's Gnd to VREFA-
    • route VDDA to VREFA+

    Again (pardon) but does not this implementation meet your desired:  "Add ZERO - board space & component cost?"

    If we assume that VDDA is at/around 3V3 - then your ADC's voltage span exceeds the 3V0 span - via your servo Ref Gen.      And is unlikely to be as accurate - yet (still) your MCU's ADC (NOW) is "Back ON the AIR" - as is the Analog Comparator - again at  NO/ZERO size - nor cost penalty!

    Your detail indeed convinces that neither the ADC nor Analog Comparators (+ possible other sub-systems) are needed for "THIS" project.      My concern is for your, "FUTURE PROJECTS - OR SPIN-OFFS!".

    I've one (last) concern - that being the "long-term" impact of running VDDA+ at/near 0V.     While "claimed ok" - I am (somewhat) doubtful that such operation has been (really) subjected to "FULL DEVICE" Test Screening/Qualification...     (this as such operation is FAR from "normal/customary" - where most such device "test/verification" really centers ... I past worked @ similar semi "giant.")

    My intent here is, "Not to torment" - but to suggest,  "Slight - cost/size FREE - Course Deviation"  -  which adds flexibility to your design while steering you BACK to the safety/comfort of the,  "herd."

  • 0 in reply to cb1_mobile
    Intellectual 520 points
    Hiya cb1!

    Thank you for your ongoing interest, thoughts, concerns, questions and suggestions!

    I am happy to explain the rationale behind the choice of VREFA- / VREAFA+ :

    1) The datasheet says that ADC inputs are limited to GNDA/VDDA with *NO* headroom tolerance whatsoever
    2) The datasheet is trying to save you grief here - ignore it at your peril, Bad Things (TM) *DO* happen when ignored
    3) The datasheet gives a maximum source impedance for driving ADC inputs - ignore this at your peril also!

    Since we a) CANNOT exceed GNDA/VDDA, even by a small amount, ever, on an ADC input and b) we MUST present a low source impedance to the ADC, the safest option is to interpose a buffer amplifier between the signal source and the ADC.

    The issue is then finding a buffer that really does go from rail to rail - most will get close, but won't actually get there. To address this, there are devices such as the LM7705 -232mV charge pump regulator specifically designed to allow an opamp to get to GND, but this presents the danger that the ADC input could drop below GNDA - indeed the saturation voltage varies as f(temperature) so whilst it might be fine at 10 degrees, it might not be at 100 degrees.

    One can infer from the datasheet that it is valid for an ADC input to exceed VREFA- / VREFA+, just not GNDA / VDDA (you will get a saturated reading, which is fine). It is therefore possible to use the full scale of the ADC, getting to "both rails" without danger of the ADC misbehaviour attendant with exceeding GNDA/VDDA rails. Most rail-to-rail opamps will get within 150mV of their rails, and using GNDA/VDDA as the supply rails for the opamps means they cannot drive a signal into the ADC that is out of spec.

    It should be clear from the fact that I have gone to the trouble of generating 150mV and 3150mV servo references on this board, that it does use the ADC in "normal" operation. This covers 99.999% of the time it is powered - the supply under those conditions is adequate to power up the reference generators.

    The usage scenario I was contemplating was the 0.001% of the time that the board is having its firmware updated - I wanted to avoid the necessity to power it using its normal supply - that the USB cable would be adequate for that purpose, but that the sole "function" of the board under those conditions was to update firmware, nothing else needs to work.

    Aside : the design spec for the input stage is thus - ADC readings between 0x000 and 0xFFF shall represent voltages between -5V and +5V, voltages past those shall saturate. The input circuit shall present a constant input impedance to the signal source of at least 100k. The input will tolerate, indefinitely, -240VDC to +240VDC / 240Vrms or -350VDC to +350VDC intermittently. The propagation delay of the input stage shall not exceed 80ns. Its output shall not exceed GNDA/VDDA and shall present a low impedance to the ADC input. [Hint - the ADC is not the only thing the input stage drives]

    Best regards,

    Pat.
  • 0 in reply to Patrick Herborn
    Guru 117855 points

    Once again - your effort & detailed description - much appreciated.       Firm/I have long used a variety of ARM Cortex  M0, M3, M4 & M7 - and have NOT had your astuteness in providing the 0V150  "boundary guardbands" (@ each end) - as you've noted.    (I believe that to be  somewhat "unusual"  - AND quite clever!    and ... subject to appropriation.)

    On several designs (multiple ARM vendors) our signal has driven (briefly) below the GNDA rail - but by less than 0V100.     And to our best knowledge - this has NOT (yet) produced (notable or lasting) "ill-effects."

    I had not sensed that your board usage would (usually) employ the servo references (which was curious) - I'm glad that you've (now) detailed that fact.

    Firm/I have long imposed a buffer-amplifier - between the external analog signals - and MCU's ADC inputs.     We - and others - have additionally found the inclusion of small value - ceramic caps - placed in close proximity to the ADC pins - most helpful...

    Thanks for (very) well "removing" the "mystery veil" - presented (initially) by your application...    Your time/effort - was & is - appreciated...

  • 0 in reply to cb1_mobile
    Intellectual 520 points

    Hiya cb1!

    Glad that I cleared up the confusion and that some good may come of that!

    With regard to ARM usage - if names like Albion, Anna and Arabella "mean anything" to you, then you have *definitely* been around ARM stuff a long time!

    And for those reading who do.... another trip even further down memory lane..... :

    LDA #247

    LDX #76

    JSR &FFF4

    JMP (&FFFC) [or JMP &D9CD]

    Kudos to anyone who remembers what that does!

    Best regards,

    Pat.

  • 0 in reply to Patrick Herborn
    Guru 117855 points

    Staff here (my small tech office) notes that they entered (that exact) ASM sequence as "Justification" for the "Dismissal of  recent  Traffic Citation." I'm "sad to report" that the FINE "Doubled."

    Neither our memory - nor our lane - extends that far...    (AT91SAMS7 was our initial device - "Won in a Seminar Contest"... Kudos free.)