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TMS570LS3137: Fapi_BlockErase() - prefetch exception

c sen
Intellectual 530 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN, UNIFLASH

Hi,

I am working on a bootloader. I copied bl_flash.c/.h and couple other related files from TI's bootloader sample.

Including F021 version 02.01.01 and linking with F021_API_CortexR4_BE.lib.

And I create the drivers and startup code with Halcogen version 3.05.

All works fine other than the fact that Fapi_BlockErase() in bl_flash.c throws prefetch exception. (jumps to prefetchEntry line)

Odd thing is Fapi_blockErase does not throw this exception when I comment out rtiStartCounter(rtiCounter_block0) in my main() .

I need to have RTI for other requirements. Not sure what to make out of this symptom.

How could RTI_counter0 running conflict with flash_erase operation and throw prefetch?

thank you,

  • 0
    TI__Guru**** 192486 points
    Hello,

    If you want to erase the sector which is in the same bank of your code, you have to copy the flash-operation related code to SRAM and execute those code in SRAM. Otherwise, you will get problem.

    BTW, there is new version HALCoGen available: v4.07
  • 0 in reply to QJ Wang
    Intellectual 530 points
    oh yes, flash related code and F021 library are copied to SRAM and run from SRAM. Exactly the way it is done in Bootloader example done by TI.
    No problem in that matter.

    Fapi_BlockErase() in bl_flash.c throws prefetch exception. (jumps to prefetchEntry line)

    Odd thing is Fapi_blockErase does not throw this exception when I comment out rtiStartCounter(rtiCounter_block0) in my main() .

    I need to have RTI for other requirements. Not sure what to make out of this symptom.

    How could RTI_counter0 running conflict with flash_erase operation and throw prefetch?

    thank you,
  • 0 in reply to c sen
    Intellectual 530 points
    I run into these two posts :

    e2e.ti.com/.../662529

    e2e.ti.com/.../926522

    The first post from 2018 says:

    "It is highly recommended to disable interrupts during reprogramming. This is how all of our programmers are setup including CCS and Uniflash so the flash programming operation isn't interrupted."

    Based on the first post, interrupts (IRQ/FIQ) are not allowed while erasing a sector on the bank where my bootloader ISRs reside.
    Is this true?
    Please pay attention, my ISRs reside on sector 1 of bank 0 while i try to erase/program sector 4 of bank 0.

    Please clarify.

    background:
    ==============
    My boorloader code resides in first couple sectors of bank 0 and flash related code is already copied to RAM at startup, the way done in TI Bootloader example.
    I am trying to erase sector 4 of bank 0 and write the application binary to the sector 4 of bank 0.

    I have sci tx, rx interrupts and RTI compare 0 interrupt enabled. all these interrupts are IRQ.
    Enabling RTI compare 0 interrupt is causing prefetch abort while erasing sector 4 of bank 0.
  • 0 in reply to c sen
    TI__Guru**** 192486 points
    Hello,

    The code which will execute during flash operation (erasing/programming) should be located in another flash bank or SRAM.
    Please copy the RTI ISR to SRAM.

    Another try:
    Since LS3137 has 2 flash banks, erase the sectors in bank1 and program the application to bank1. you can execute the code in bank0, so don't need to copy code to SRAM.
  • 0 in reply to QJ Wang
    TI__Guru**** 192486 points
    Hello,

    I just tried, there is no problem to enable interrupt and run the RTI ISR in flash bank0, and erase/program bank1 at a time.