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TM4C1294NCPDT: QSSI connect to Multi Channel ADC

Calex36
Intellectual 2125 points
Part Number: TM4C1294NCPDT

I am planning to use the QSSI on the TivaC to connect a multi-channel ADC.

 

I need some help understanding Relationship between the frame sync and the data in receive mode.

What happens if the frame is longer than the data size? I checked here but wasn't clear to me.

 

Ideally I would have 4 bit wide data that is 64 bits long (256 bits per frame),

That would produce 32 bytes DMA’d direct to pin-pong ram.

 

Any app notes?

 

I have two Tiva dev boards so are going to try some things so any examples that would help me get started with evaluating this would be much appreciated :)

  • 0
    TI__Guru 72500 points

    For the SSI you initiate reads by writing to the transmit FIFO. In Quad SSI mode, you write the upper 4 bits of the 16 bit transmit FIFO (bits 15:12) with three bits indicating the mode and one bit for the end of frame indicator. To read 32 bytes in quad mode you would write (or have the uDMA write) 31 times the value 0x40xx and then write one time the value 0x50xx (the xx, lower 8 bits are don't care). The FSS signal goes low at the start of the first transmission and then goes high after the end of the last transmission.

  • 0 in reply to Bob Crosby
    TI__Intellectual 2125 points
    Hi Bob,

    Thank you for answering my question, Is there any example code that I can run on my Tiva dev kit that represents the above.
  • 0 in reply to Bob Crosby
    Prodigy 20 points

    This answer deals with writes (transmit data from the TIVA) where the TIVA is a bus master.

    My questions was about reads, when the TIVA is a slave device, the clock and frame are supplied externally in QSSI mode.

    In our application the TIVA never sends data.

    All recieved data goes into DMA

    Regards,

    Jason Morgan

    Sentec.

  • 0 in reply to Calex36
    TI__Guru 72500 points
    Here is a thread about using QSSI on an external Flash:
    e2e.ti.com/.../451470
  • 0 in reply to Jason Morgan
    TI__Guru 72500 points
    When the QSSI is a slave, the FSS signal acts as a slave chip select.

    Do you really mean the TM4C will be the slave? In quad mode, the transfer is half duplex. The master can read or write and the data pins become inputs or outputs respectively. However, the master stays the master and provides the clock and FSS signal even when reading.

    Are you planning on connecting two TM4C together, one as master and the other slave? If not, what device will be the master?
  • 0 in reply to Bob Crosby
    Prodigy 20 points

    The master is an ADC, e.g. the AD7779 (I'm sure that was mentioned in the first post, but forgive me if it was not)

    The ADC output a clock and frame.

    If the TIVA can't be an SPI slave then we have a problem......

    May have to consider a different CPU!

  • 0 in reply to Jason Morgan
    TI__Intellectual 2125 points
    Hi Jason,

    The Tiva QSSI works with both Master or slave operation,
    We'll have comment soon on how will work with master ADC
  • 0 in reply to Jason Morgan
    TI__Guru 72500 points

    Hi Jason,

    I looked at the Analog Devices datasheet for the AD779. I assume you want to use the "data output" interface as a master quad SPI. The TM4C1294 can capture the data, the issue is synchronization. The DRDY- signal does not act as a CS- signal. What is not clear to me is if the DCLK is free running, or only active when there is data to shift out. The timing diagram for the reset and synchronization signals does not show the DCLK signal. (Maybe it is not active for that first DRDY- pulse.)

    The QSSI on the TM4C does not need the FSS signal. If the DCLK from the ADC only toggles when there is data to output (not free running),  then you can start the QSSI on the TM4C as a slave and then send the SYNC_IN signal to the ADC to start the process. However, this statement on page 57 of the AD779 datasheet makes me think DCLK is free running.

    Sorry, to give you a better answer requires a knowledge of a competitor's part that I do not have.