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TMS570LS3137: BANK0 sector erase problem

BarematalProgrammer
Expert 1715 points

Part Number: TMS570LS3137

Hello  ,

This Query is with Boot Loader and usage of F021_API_CortexR4_BE_V3D16.lib , how to load the F021_API_CortexR4_BE_V3D16.lib dynamically in the RAM and execute not during power up sequence .

I have no errors erasing Sector 15 through 27 of FLASH  BANK 1 .

Boot Loader is located and running at Sector 0 through Sector 7 of FLASH BANK 0, 

During erase of Sectors 8 - 15 , there is no source code in these sectors located in FLASH BANK 0 . While Erase of  Sectors of Bank 0 --- System Reset occurs at following FAPI instruction .

status=Fapi_setActiveFlashBank((Fapi_FlashBankType)0);

I have set the TMS570LS3137 in Safe Mode ( Enabling all safety features ) and also perform all safety library startup code .

And also please let me know if it is Mandatory to copy the FLASH API to RAM and execute Erase and Write from RAM for BANK 0.

Also Please help me with source code how to load FLASH API library into RAM (.test , .const )  at Run-time as the SRAM test would fail if we did load the FLASH API library into RAM initially itself as in .cmd file .

I want to do the following copy process at run-time after completion of SRAM test .

load = FLASH_API, run = SRAM, LOAD_START(api_load), RUN_START(api_run), SIZE(api_size)

Is there any errata that I should respect while doing erase of SECTORS 8 through 15 of FLASH BANK 0

Following image shows registers of FLASH WRAPPER before reset occurs

  • 0
    TI__Guru**** 201376 points
    Hi Chandre,

    1. To erase/program the sectors in bank0, you have to execute the flash API related code from a separate flash bank, or from SRAM. To copy the sections to SRAM:
    a. define the output sections which includes all the API related function, then allocate them to flash for loading and SRAM for run
    b. in main() or startup(), please copy those output sections to SRAM (please refer to the example in bootloader)

    Copying only the F021 APIs to SRAM is not enough. The following functions should be copied to RAM too:
    a. Fapi_UserDefinedFunctions.obj
    b. functions who call the F021 APIs
    So the output sections should include those objects.

    2. It is nice to copy the variables or constants (for example flash sectors defined in my flash_defines.h) to SRAM too.
    .const : {} palign=8 load=FLASH0 |FLASH1, run = SRAM, LOAD_START(constLoadStart), RUN_START(constRunStart), SIZE(constLoadSize)
  • 0 in reply to QJ Wang
    Expert 1715 points

    Hi Mr.QJ Wang ,


    1. Appreciate for taking time and explaining process to erase Bank 0 in detail . Is there a possibility not Entire Flash Bank 0 is locked  , if only SECTORS that are used is locked. 

    2. If I load the FLASH API to RAM The Safety application I am implementing has SRAM_ResetTest and the code is always hang at 

    /* Wait for PBIST for PBIST and STC ROM to be completed */
    while((systemREG1->MSTCGSTAT & 0x1U) == 0U) {};

    3. Is there a work around for SRAM test not to fail .

    4. I understand per requirement to run the FLASH API from RAM and I am following the Boot loader example , but I do not have flexibility to use RAM load and RAM execute in my SAFETY APPLICATION .

  • 0 in reply to QJ Wang
    Expert 1715 points

    Hi Mr.QJ Wang ,


    1. Appreciate for taking time and explaining process to erase Bank 0 in detail . Is there a possibility not Entire Flash Bank 0 is locked  , if only SECTORS that are used is locked. 

    2. If I load the FLASH API to RAM The Safety application I am implementing has SRAM_ResetTest and the code is always hang at 

    /* Wait for PBIST for PBIST and STC ROM to be completed */
    while((systemREG1->MSTCGSTAT & 0x1U) == 0U) {};

    3. Is there a work around for SRAM test not to fail .

    4. I understand per requirement to run the FLASH API from RAM and I am following the Boot loader example , but I do not have flexibility to use RAM load and RAM execute in my SAFETY APPLICATION .

  • 0 in reply to BarematalProgrammer
    TI__Guru**** 201376 points
    Hello Chandre,

    1. Clearing PROTL1DIS bit of FBPROT will enable the bank protection from writing. The Bank Sector Enable register (BSE) is used to enable/disable the sectors for program or erase access. The default setting after reset is "disabled"

    2. It is better to run SRAM_ResetTest before copying flash API from flash to SRAM. The contents of the selected memory before the test will be completely lost after PBIST test. Your code must take care of data backup if running the flashing copy before the PBIST test. Typically the PBIST tests are carried out at the beginning of Application software.

    3. You need to wait for the PBIST self-test done by polling MSTDONE bit of MSTCGSTAT register in System Module. If it loops forever, you need to figure out what causes the problem.
    a. Is PBIST sequence correct?
    b. Is the selected memory implemented in your device?
    c. Is the test algorithm allowed for your selected memory?
    d. Is OVER is programmed before RAM group selection: RINFOL, RINFOU?
    If the same code works on another board, the silicon on your failed board might be damaged.

    4. In your application, you can copy code to SRAM and execute the code from SRAM. This should not be affected by the bootloader.
  • 0 in reply to QJ Wang
    Expert 1715 points

    Hello Mr.Qj Wang ,

    Flash Memory Map is as follows ( this is different from what is recommended to have boot-loader  from 0x00000000 to 0x00020000 ):

    0x00000000 to 0x000A0000 --- SAFETY CRITICAL Application software with strict SIL2 certification ( I am using boot loader to erase and re-write these locations )

    0x000C0000 to 0x000E0000 --- Boot Loader software non safe ( I am using boot loader running from this location to erase and write application mentioned above)

    The SAFETY CRITICAL Application source code I am working with has strict  SIL2 rules so it has all exceptions enabled and it has dedicated flash address 0x00000000 to 0x000A0000 mapped as SIL2 SAFETY CRITICAL software location , I am not allowed to relocate it to different address from these FLASH Locations ( I am using using Boot-loader that I will rewrite application ).

    If I move the SIL2 certified Source code from 0x00000020 to say beginning 0x00040000 the _undef Exception occurs . ; reset the abort stack as this handler is not re-entrant and is left by longjmp in some cases

    Currently my boot-loader project located at 0x000C0000 has Debug build and It fails to re-write IVT  address 0x00000000 to 0x00000020  works for all other 0x00000020 to 0x00300000  Sectors 0 through Sector 27 , I know that .intvecs is mapped to  address 0x00000000 to 0x00000020  Does this imply never erase .intvecs ? , is there a workaround as we need this for our project .

    Appreciate your effort for providing an extensive explanation that fixed all the issues ( other than Sector 0). I have now disabled the SRAM PBIST Tests and Flash PBIST tests . 

    I have now implemented controlled copy of (.text,.const of Flash API Library ) into RAM and also setting PROTL1DIS bit of FBPROT  ( implemented as  Flash_registers.FBPROT=1; ) .

    flashAPI :
    {
    --library= F021_API_CortexR4_BE_V3D16.lib < Utilities.GetNumberOfSectors.obj > (.text:Fapi_getNumberOfBankSectors)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.InitializeFlashBanks.obj > (.text:Fapi_initializeFlashBanks)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.SetActiveBank.obj > (.text:Fapi_setActiveFlashBank)
    --library= F021_API_CortexR4_BE_V3D16.lib < Program.obj > (.text:Fapi_issueProgrammingCommand)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.EnableMainSectors.obj > (.text:Fapi_enableMainBankSectors)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.Common.obj > (.text:_Fapi_enterMarginMode)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.MarginByByte.obj > (.text:Fapi_doMarginReadByByte)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.IssueFsmCommand.obj > (.text:_Fapi_issueFsmCommand)
    --library= F021_API_CortexR4_BE_V3D16.lib < Utilities.CalculateFletcher.obj > (.text:Fapi_calculateFletcherChecksum)
    --library= F021_API_CortexR4_BE_V3D16.lib < Async.WithAddress.obj > (.text:Fapi_issueAsyncCommandWithAddress)
    --library= F021_API_CortexR4_BE_V3D16.lib < Utilities.WaitDelay.obj > (.text:Fapi_waitDelay)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.Common.obj > (.text:_Fapi_exitMarginMode)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.FlushPipeline.obj > (.text:Fapi_flushPipeline)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.InitializeFlashBanks.obj > (.text:_Fapi_divideUnsignedLong)
    --library= F021_API_CortexR4_BE_V3D16.lib < Utilities.CalculateEcc.obj > (.text:Fapi_calculateEcc)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.ScaleFclk.obj > (.text:_scaleEEFclk)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.ScaleFclk.obj > (.text:_scaleMainFclk)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.WdService.obj > (.text:_Fapi_checkWdService)
    --library= F021_API_CortexR4_BE_V3D16.lib < BlankCheck.ByByte.obj > (.text:Fapi_doBlankCheckByByte)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.EnableEepromSectors.obj > (.text:Fapi_enableEepromBankSectors)
    --library= F021_API_CortexR4_BE_V3D16.lib < Read.LoopByByte.obj > (.text:_Fapi_loopRegionForValueByByte)
    --library= F021_API_CortexR4_BE_V3D16.lib < FlashStateMachine.EnableEepromSectors.obj > (.text:_Fapi_EnableSectors)

    boot_flash.obj(.bss,.data,.text,.const)
    boot_erase.obj(.bss,.data,.text,.const)
    Boot_Can_Upd.obj(.bss,.data,.text,.const)
    Boot_Emif_Write_Data.obj(.bss,.data,.text,.const)


    } load = FLASH_API, run = SRAM, LOAD_START(UNSAFE_LOAD_START), RUN_START(UNSAFE_RUN_START), SIZE(UNSAFE_RUN_SIZE)

    ;-------------------------------------------------------------------------------
    ;
    ; Copy the Flash API from flash to SRAM.
    ;
    ;
    .def _Boot_copyAPI2RAM_
    .asmfunc

    _Boot_copyAPI2RAM_

    .ref UNSAFE_LOAD_START
    flash_load .word UNSAFE_LOAD_START
    .ref UNSAFE_RUN_START
    flash_run .word UNSAFE_RUN_START
    .ref UNSAFE_RUN_SIZE
    flash_size .word UNSAFE_RUN_SIZE

    ldr r0, flash_load
    ldr r1, flash_run
    ldr r2, flash_size
    add r2, r1, r2
    copy_loop1:
    ldr r3, [r0], #4
    str r3, [r1], #4
    cmp r1, r2
    blt copy_loop1
    bx lr

    .endasmfunc

  • 0 in reply to BarematalProgrammer
    TI__Guru**** 201376 points
    Hello Chandre,

    Your bootloader is not located in sector0, the application has to be programmed by JTAG for the first time. Everytime the application executes first after reset (SW, CPU, nPORRST etc), and jump to bootloader conditionally (command from outside).

    Is your bootloader able to erase other sector, for example sector 13/14?
  • 0 in reply to QJ Wang
    Expert 1715 points
    Hi Mr.QJ Wang ,

    The _undef Exception occurs if the jump address (of _c_int00 ) is beyond sector 0 ie.... 0x00008000 address on power up of micro controller .

    I want to control the SECTOR 0 of BANK 0 . Can you help me explaining first 20 WORDS of INTERPPUT VECTOR TABLE .

    The source code generates _c_int00 at address 000052b4 but the FLASH location that points to _c_int00 is as EA0014AB

    what does the first 20 words provided in the following mean how to decode these

    EA0014AB EA03FFFE EA03FFFE EA03FFFE EA03FFFE EAFFFFFE E51FF1B0 E51FF1B0


    Thanks in advance,
  • 0 in reply to BarematalProgrammer
    TI__Guru**** 201376 points

    Hello Chandren,

    When an exception occurs, the processor must execute handler code that corresponds to the exception. The location in memory where the handler is stored is called the exception vector. In the ARM Cortex-R4/R5, exception vectors are stored in a table, called the exception vector table. The table contains branch instructions that direct the core to the full exception handler.

    The base address for exception vector on ARM Cortex-R4/5 is 0x00000000 which is not programmable.

    This is the definition of the exception vector (ARM Cortex-R4 TRM):

    EA0014AB EA03FFFE EA03FFFE EA03FFFE EA03FFFE EAFFFFFE E51FF1B0 E51FF1B0

    1. The first word is the branch instruction to _c_int00()  -- b _c_int00

    2. the 2nd word ~ 5th word are the instructions to branch to itself

    3. The 6th is reserved

    4. The last two are for IRQ and FIQ

  • 0 in reply to QJ Wang
    Expert 1715 points

    Hello Mr.QJ Wang ,

    I appreciate you taking time to explain in details the first 8 words .

    Following is my understanding .

    Opcode EA stand for BRANCH

    EA - - BRANCH instruction followed by 3 bytes of relative address to branch from current address     (  in multiples of 32 bits as TMS570LS3137 is 32 bit controller) .

    Now I understand that the EA0014AB refer to branch relative address from current address to so many words(32bits or 4 bytes) as the Program Counter should load _c_int00 at 0x000052AC .
    ENTRY POINT SYMBOL: "_c_int00" address: 000052AC


    For the EA03FFFE EA03FFFE EA03FFFE EA03FFFE EAFFFFFE I understand it is as follows when we break down to OPCODE


    here BAL here ; BRANCH assembles to 0xEAFFFFFE (note effect of PC offset).

    Thanks again ,