TMS570LS3137: checkRAMECC: Writing to ECC memory location

Hello,

This question is related to below set of instructions in checkRAMECC() in sys_selftest.c file generated by HALCOGEN version 4.7:

/* Force a single bit error in both the banks */
_coreDisableRamEcc_();
tcramA1bitError ^= 1U;
tcramB1bitError ^= 1U;
_coreEnableRamEcc_();

When toggling BIT-0 of RAM ECC location 0x08400000 i code see other bits of the ECC location also changing: Below is the observed behaviour:

1. Just before toggling, i could see 0x0C0C0C0C data at 0x08400000 in memory browser.

2. after toggling bit-0, i see the value at 0x08400000 as 0x0D0D0D0D. 

Why BIT-8, BIT-16 and BIT-24 are also changing? Can you please help me to understand this behaviour and please provide me some documentation related to this behaviour.

Thanks in advance.

Below is a snippet from SPNU499C document:

6.1.2 Main Features
The main features of the tightly-coupled RAM interface module are:
• Controls read/write accesses to the data RAM
• Decodes addresses within the memory region allocated for the RAM
• Supports read and write accesses in 64-bit, 32-bit, 16-bit or 8-bit access sizes
– Does not support bit-wise operations

Regards,

Kalyan