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CCS/TM4C1290NCPDT: TM4C129 EPI HB8 ADMUX not working

Fayez chayab
Prodigy 20 points
Part Number: TM4C1290NCPDT

Tool/software: Code Composer Studio

Hello,

I've been trying to get the EPI on the TM4C129 working in muxed 8bit host bus mode but having zero luck. Snippets of the code are below, please let me know what I'm doing wrong. On the scope I monitor the AD0, ALE, WRn, RDn and nothing is toggling.

///////////////////////////////////////////////

//from the linker file

//////////////////////////////////////////////

--retain=g_pfnVectors

#define NOINIT_RAM_SIZE 0x10
#define FPGA_BASE 0xA0000000

MEMORY
{
    FLASH (RX)                     : origin = 0x00004400,             length = 0x00100000 - 0x4400
    SRAM (RWX)                     : origin = 0x20000000,             length = 0x00040000 - NOINIT_RAM_SIZE
    NOINIT_RAM (RWX)             : origin = end(SRAM),             length = NOINIT_RAM_SIZE
    /* Application uses external FPGA memory mapped resigters */
    FPGA (RWX)                     : origin = FPGA_BASE,             length = 0x00010000
}


SECTIONS
{
    .intvecs:   > 0x00004400
    .text   :   > FLASH
    .const  :   > FLASH
    .cinit  :   > FLASH
    .pinit  :   > FLASH
    .init_array : > FLASH

    .vtable :   > 0x20000000
    .data   :   > SRAM
    .bss    :   > SRAM
    .sysmem :   > SRAM
    .stack  :   > SRAM
    .external : > FPGA

    .noinit :   > NOINIT_RAM, type = NOINIT
}

__STACK_TOP = __stack + 512;

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//EPI initilization

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The following specifies the GPIO pins used by the EPI bus when
// configured in HostBus8 mode. using AD[0..7] & A[8..15], WRn, RDn & ALE
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define EPI_PORTA_PINS          0xC0    //pins[7:6] used for Addr A[9:8]
#define EPI_PORTB_PINS          0x04    //pin[2] used for RD_strobe
#define EPI_PORTC_PINS          0xF0    //pins[4:7] used for AddrData AD[7:4]
#define EPI_PORTD_PINS          0x00    //not used by EPI
#define EPI_PORTE_PINS          0x00    //not used by EPI
#define EPI_PORTF_PINS          0x00    //not used by EPI
#define EPI_PORTG_PINS          0x03    //pins[0:1] used for Addr A[11:10]
#define EPI_PORTH_PINS          0x0F    //pins[3:0] used for AddrData AD[3:0]
#define EPI_PORTJ_PINS          0x00    //not used by EPI
#define EPI_PORTK_PINS          0x00    //not used by EPI
#define EPI_PORTL_PINS          0x07    //pins[2:0] used for Addr[18:16]
#define EPI_PORTM_PINS          0x0F    //pins[0:3] used for Addr[15:12]
#define EPI_PORTN_PINS          0x00    //not used by EP
#define EPI_PORTP_PINS          0x0C    //pin[2] used for WR_strobe & pin[3] used for ALE
#define EPI_PORTQ_PINS          0x00    //not used by EPI

    // Enable all GPIO banks.
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

/*
    GPIOPadConfigSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTB_BASE, EPI_PORTB_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTB_BASE, EPI_PORTB_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTD_BASE, EPI_PORTD_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTD_BASE, EPI_PORTD_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTH_BASE, EPI_PORTH_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTH_BASE, EPI_PORTH_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTK_BASE, EPI_PORTK_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTK_BASE, EPI_PORTK_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTL_BASE, EPI_PORTL_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTL_BASE, EPI_PORTL_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTM_BASE, EPI_PORTM_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTM_BASE, EPI_PORTM_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTN_BASE, EPI_PORTN_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTN_BASE, EPI_PORTN_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTP_BASE, EPI_PORTP_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTP_BASE, EPI_PORTP_PINS, GPIO_DIR_MODE_HW);
    GPIOPadConfigSet(GPIO_PORTQ_BASE, EPI_PORTQ_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTQ_BASE, EPI_PORTQ_PINS, GPIO_DIR_MODE_HW);
*/
    //
    // Enable pin PH0 for EPI0 EPI0S0
    //
    MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0);
    GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_0);
    //
    // Enable pin PH1 for EPI0 EPI0S1
    //
    MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1);
    GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_1);
    //
    // Enable pin PH2 for EPI0 EPI0S2
    //
    MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2);
    GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_2);
    //
    // Enable pin PH3 for EPI0 EPI0S3
    //
    MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3);
    GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_3);
    //
    // Enable pin PC7 for EPI0 EPI0S4
    //
    MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);
    //
    // Enable pin PC6 for EPI0 EPI0S5
    //
    MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);
    //
    // Enable pin PC5 for EPI0 EPI0S6
    //
    MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
    //GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);
    //
    // Enable pin PC4 for EPI0 EPI0S7
    //
    MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);
    //
    // Enable pin PA6 for EPI0 EPI0S8
    //
    MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
    GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);
    //
    // Enable pin PA7 for EPI0 EPI0S9
    //
    MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
    GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);
    //
    // Enable pin PG1 for EPI0 EPI0S10
    //
    MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
    GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);
    //
    // Enable pin PG0 for EPI0 EPI0S11
    //
    MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
    GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);
    //
    // Enable pin PM3 for EPI0 EPI0S12
    //
    MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);
    //
    // Enable pin PM2 for EPI0 EPI0S13
    //
    MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);
    //
    // Enable pin PM1 for EPI0 EPI0S14
    //
    MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);
    //
    // Enable pin PM0 for EPI0 EPI0S15
    //
    MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);
    //
    // Enable pin PL0 for EPI0 EPI0S16
    //
    MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);
    //
    // Enable pin PL1 for EPI0 EPI0S17
    //
    MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);
    //
    // Enable pin PL2 for EPI0 EPI0S18
    //
    MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);
    //
    // Enable pin PB3 for EPI0 EPI0S28
    //
    MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
    GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);
    //
    // Enable pin PN2 for EPI0 EPI0S29
    //
    MAP_GPIOPinConfigure(GPIO_PP2_EPI0S29);
    GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2);
    //
    // Enable pin PN3 for EPI0 EPI0S30
    //
    MAP_GPIOPinConfigure(GPIO_PP3_EPI0S30);
    GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3);

    // Enable the EPI peripheral
     MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
    // Set the EPI operating mode for FPGA iFace
    // The values used here set the EPI to run at the system_clock/16 = 7.5MHz
    // with first 8 bits of AddrData muxed
    // two wait states for rd/wr, this is wait 0 which is two EPI clocks
    EPIModeSet(EPI0_BASE, EPI_MODE_HB8);
    EPIDividerSet(EPI0_BASE, 16);
    //EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0 |
                    //EPI_HB8_RDWAIT_0 | EPI_HB8_WORD_ACCESS), 0);
    EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_0 |
                    EPI_HB8_RDWAIT_0), 0);
    EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_64KB | EPI_ADDR_PER_BASE_A);

///////////////////////////////////////////////////////////////////////////////
// simple test usage
///////////////////////////////////////////////////////////////////////////////

#define FPGA_BASE 0xA0000000

volatile uint16_t *FPGAptr = ((uint16_t  *)FPGA_BASE);

int main(void)

{
    uint32_t i;

    for (i = 0; i < 32768; i++)
    {
        FPGAptr[i] = i;
    }

    for (i = 0; i < 32768; i++)
    {
        ptr[i] = FPGAptr[i];
    }
}

  • 0
    TI__Guru*** 135225 points

    Hello Fayez,

    Looking at our EPI example, I think an issue you have is your repeated calls of GPIOPinTypeEPI.

    I think you may be undoing other pin settings with these.

    It looks like the proper method is:

        //
    // Configure the GPIO pins for EPI mode.  All the EPI pins require 8mA
    // drive strength in push-pull operation.  This step also gives control of
    // pins to the EPI module.
    //
    GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
    GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
    GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
    GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
    GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
    GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);
    GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);
    GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);
    GPIOPinTypeEPI(GPIO_PORTN_BASE, EPI_PORTN_PINS);
    GPIOPinTypeEPI(GPIO_PORTP_BASE, EPI_PORTP_PINS);
    GPIOPinTypeEPI(GPIO_PORTQ_BASE, EPI_PORTQ_PINS);

    Note that the GPIOPinTypeEPI call will handle both GPIODirModeSet and GPIOPadConfigSet

    Therefore you can get rid of all the lines of code doing this:

     GPIOPadConfigSet(GPIO_PORTQ_BASE, EPI_PORTQ_PINS, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
    GPIODirModeSet(GPIO_PORTQ_BASE, EPI_PORTQ_PINS, GPIO_DIR_MODE_HW);

    See if the changes for GPIOPinTypeEPI are sufficient to get your outputs going.

  • 0 in reply to Ralph Jacobi
    Prodigy 20 points

    Hi Ralph,

    Thanks for replying.

    As you can see in the code snippet all these lines are commented out /* ...*/. it was one of my tries, then i tried setting each pin individually.  Both didn't work. Now i tried your suggestion above and that also didn't work.

    after going thru all the settings again i noticed i used one wrong setting. originally i had

     EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_64KB| EPI_ADDR_PER_BASE_A);

    changing it to the proper

     EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_64KB | EPI_ADDR_PER_BASE_A);

    Now the lines are toggling but i ran in to another issue. Accessing the first 32K worked but if i try to access any address above that i get stuck in an ISR fault. the fault ISR happens directly after i try to read

     ptr = FPGAptr[0x8000]; //which is first byte after 32K

    below are the fault registers

    NVIC_FAULT_STAT    0x00008200    Configurable Fault Status [Memory Mapped]    
    NVIC_HFAULT_STAT    0x40000000    Hard Fault Status [Memory Mapped]    
    NVIC_MM_ADDR    0xA0010000    Memory Management Fault Address [Memory Mapped]    
    NVIC_FAULT_ADDR    0xA0010000    Bus Fault Address [Memory Mapped]    

    the above is indicating that i'm trying to read the byte right above 64K which would cause a fault, since length was declared to be 0x00010000. Any clue why this would be happening when I believe that I'm accessing the 1st byte after 32K.


    Thanks in advance,

    Fayez

  • 0 in reply to Fayez chayab
    TI__Guru*** 135225 points

    Hello Fayez,

    Following along with our Fault Diagnosis app note: http://www.ti.com/lit/an/spma043/spma043.pdf

    It looks like the fault is caused by the following case:

    Imprecise Data Bus Error

    A data bus error has occurred, but the return address in the
    stack frame is not related to the instruction that caused the error.

    When this bit is set, a fault address is not written to the FAULTADDR
    register.
    This fault is asynchronous. Therefore, if the fault is detected when the
    priority of the current process is higher than the bus fault priority, the
    bus fault becomes pending and becomes active only when the processor
    returns from all higher-priority processes. If a precise fault occurs before
    the processor enters the handler for the imprecise bus fault, the handler
    detects that both the IMPRE bit is set and one of the precise fault status
    bits is set.
    This bit is cleared by writing a 1 to it.

    From what I am seeing on my searches regarding this error, pretty much every circumstance it occurred was due to accessing a peripheral that was not properly enabled before. At a glance through your code, however, I do not see any peripherals that could be a culprit. As I don't have your full code to review I would recommend you look at what additional peripherals may start to be accessed when you read from beyond 32k and see if there is a missed call for one of them.