RM48L540: How to enable the division by zero bit to generate an undefined instruction exception ?

Eric MONTAROU

Part Number: RM48L540

Hello,

in my software a division by zero doesn't generate an undefined instruction exception.

In the cortex R4 Reference Manual there is a DZ (divide by zero) bit to generate an undefined instruction exception, in the System Control Register. By default this bit is zero (do not generate an Undefined instruction exception).

In the RM48 Reference Manual I don't find the DZ bit.

How to generate an exception when I divide a value by zero ?

Thanks

Eric

over 6 years ago

0 Miro over 6 years ago

TI__Mastermind 21425 points

Hello,

I found a thread similar to yours. Please check whether it helps.

Help:TMS570LS3137 No Divide zero abort - Arm-based microcontrollers forum - Arm-based microcontrollers...

e2e.ti.com

I read the DDI0363G_cortex_r4_r1p4_trm4.pdf ,have some question about DZ bit(Divide of Zero) of System Control Register .If i set 1 to DZ bit.Then do: U8 DIVIDE_ZeroTest

0 Eric MONTAROU over 6 years ago in reply to Miro

Prodigy 40 points

The software is already written in C language and I use the symbol / to divide. Divisions are sometimes realized in libraries that I can't change.

Best regards

Eric

0 Eric MONTAROU over 6 years ago in reply to Miro

Prodigy 40 points

Hello

DZ bit is enable by these lines (from udiv.asm)

MRC p15, #0,r3,c1,c0,#0
orr r3,r3,#0x80000
MCR p15, #0,r3,c1,c0,#0

I have included these lines in my software and it works fine for integer values. I have an exception if I divide by zero an integer.

However it doesn't work for float values, I don't have an exception.

How to have an exception by dividing a float value by zero ?

Thanks

Eric

0 Sunil Oak over 6 years ago in reply to Eric MONTAROU

TI__Mastermind 49120 points

Eric,

There is a secondary auxiliary control register which has a bit called DZC. This bit is 0 by default, which masks the output of a floating-point divide-by-zero exception. This bit must be set to '1' to enable the output of this exception. See the Cortex-R4F TRM for more details.

Regards, Sunil