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TMS570LC4357: CRC controller module issue with Full CPU mode

Salyl Bhagwat
Prodigy 190 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN,

Hi there,

I'm seeing that CRC computation in Full-CPU mode is not matching SW-only and Semi-CPU CRC computation.

Here are some details:

I've been trying to profile the CRC computation times for areas in flash using some SW implementations and comparing them against CRC HW module in TMS570. Based on the app notes, HW module clearly is much faster so I wanted to test full-/Semi-Auto modes (that uses the CRC6)4 first before finalizing a solution.

I used the pseudo code based on HDL in section 18.2.3 to compare results computed by Full-/Semi-Auto modes. However, when I run them for a very short size of 640 bytes of flash content, I get different results between SW implementation (CRC64 based on 18.2.3) and Full-CPU mode. SW implementation (CRC64 based on 18.2.3) results match Semi-CPU mode.

Why this difference for Full-CPU mode? Is there any known issue related to Full-CPU mode?

I'm using the exact sequence as described in the TRM, app notes and Halcogen code.

Thanks,

Salyl

  • 0
    Prodigy 190 points

    Also, I looked at the SPNA235 (from August 2016). In this section 3.4 (Full-CPU Mode), it states "The full CPU-Mode example utilizes the function provided by HALCoGen to access the DMA module". This is an error, right?

    My understanding (based on TMS570 TRM and HALCoGen reference code) is that in Full-CPU mode we write 64-bit values to PSA_SIGREGx (e.g. API is crcSigGen) via CPU/SW. Is there any additional sequence required in between every write to this register to ensure we don't overwrite before previous computation is completed?

    Best regards,

    Salyl

  • 0 in reply to Salyl Bhagwat
    TI__Mastermind 49120 points

    Hi Salyl,

    The only tricky thing about the full-CPU mode is to calculate the address where the 64-bit write occurs. Are you using the crcSignGen() function generated by HALCoGen? Also an issue could be with the offline calculation of the expected CRC-64 values.

    See this post for more information on offline CRC calculations: e2e.ti.com/.../2831050

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 190 points

    Hi Sunil,

    Yes, I'm using crcSignGen function generated by HalCoGen. Please note that Semi-CPU mode's calculation of CRC matches the calc_crc64's calculation of CRC. Only the Full CPU mode doesn't match. To simplify debugging, I used only 640 bytes of flash content for SW-only, Full CPU and Semi CPU modes.

    Best regards,

    Salyl

  • 0 in reply to Salyl Bhagwat
    Prodigy 190 points

    Hi Sunil,

    Just to make things very clear, I re-did this using 1 sector-size for SW-only, Full CPU and Semi CPU modes. I set the sector size to 1024 bytes and pattern count as 128 and sector count as 1 (for semi CPU mode. for Full CPU pattern count and sector count are set to 0). Even in this case, I got SW-only and Semi CPU mode results match but Full CPU did NOT match. In both Full and Semi CPU mode the destination address is the same. I also used channel 0 for both tests and channel was reset before each test.

    Best regards,

    Salyl

  • 0 in reply to Salyl Bhagwat
    TI__Mastermind 49120 points

    Hi Salyl,

    There is probably an issue with the write to the PSA SIGREGx. Can you upload your code that includes the CPU writes to these registers for the full-CPU mode?

    Also see this post that explains another peculiarity with the TMS570 CRC-64 implementation: 

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 190 points

    Hi Sunil,

    Interesting information. Thanks for these details. Let me assimilate it and get back to you. In the mean time, I need some clarification:

    Does this mean that the algorithm at section 18.2.3 of the TMS570LC4357 TRM matches the Semi CPU mode computation without need the swapping operations on the data and the results? Does this also mean that the information you have mentioned here is specific to Full CPU mode only?

    Best regards,

    Salyl

  • 0 in reply to Salyl Bhagwat
    TI__Mastermind 49120 points

    Hi Salyl,

    Yes, the CPU writes to the PSA SIGREGx registers only when using full-CPU mode.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 190 points

    Thanks Sunil. You might want to update the documentation and/or HalCoGen code to indicate the swapping issue because this doesn't seem to be mentioned in TRM or app note or the reference code.

    Best regards,

    Salyl