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TM4C1294NCPDT: Direct DMA transfer from EPI interface to SPI interface

Ali Naseri
Prodigy 180 points
Part Number: TM4C1294NCPDT

Hello,

I want to send data from an external SD-RAM, which is connected to the EPI interface, into the SPI FIFO buffer.

Now you can access the SDRAM directly by its address range if it is addressed correctly via the EPI API and the linker file.

But if you do a non-blocking read on the SDRAM, it will be done via DMA according to the datasheet.

If I want to transfer data from SDRAM via DMA into the SPI buffer and enter the address range of the SDRAM as source in the function "MAP_uDMAChannelTransferSet", would it work? Because here the DMA unit is used twice at the same time.

 MAP_uDMAChannelTransferSet(UDMA_CHANNEL_SSI1TX | UDMA_PRI_SELECT,
                                   UDMA_MODE_BASIC, (void *)(pointerToExtSDRAM),
                                   (void *)(SSI1_BASE + SSI_O_DR),
                                   ui16transferByteCount);

The important point is, that this operation should be non-blocking so the core is not stalled, otherwise it is useless.



with regards

Ali Naseri

  • 0
    TI__Guru*** 134985 points

    Hello Ali,

    Ali Naseri said:
    I want to send data from an external SD-RAM, which is connected to the EPI interface, into the SPI FIFO buffer.

    So if I am understanding here right, you are trying to:

    1) Read data from SDRAM with the EPI

    2) Store data from SDRAM into EPI FIFO

    3) Transmit data from EPI FIFO with SSI directly with from the EPI FIFO?

  • 0
    Guru 117855 points

    Hello,

    While poster's objective is well explained & makes sense generally - does it not, "Fail in Practice" due to the "so very small size" of the "SPI FIFO?"    Such forces many very short (i.e. size limited) transactions - which prove inefficient due to the "overhead demands" - forced by the µDMA upon each/every such transaction.

    Note that the µDMA may support transaction numbers reaching to 1024 - can greatly reducing that number prove wise?

    Should poster's major objective be, "Avoiding core stalling" then that (may) be achievable - but at the cost of "slowed & choppy" SPI transactions.    (vendor approval is sought to confirm that the method (can) succeed...)

  • 0 in reply to Ralph Jacobi
    Prodigy 180 points

    yes, this is my objective, transmit data (for example 500 Kbyte) from the external SD-RAM to the FIFO of the SSI via DMA automatically and non-blocking with only one command. The speed of the data transfer should be the speed of the SSI interface to avoid buffer overflow of the FIFO.

  • 0 in reply to Ali Naseri
    TI__Guru*** 134985 points

    Hello Ali,

    After some discussions, we think that it may be possible with careful configuration.

    The FIFO for both EPI and SSI are 8 deep - so that alignment will help here. 

    What should be able to work is to use the SPI uDMA to read from EPI FIFO, and EPI uDMA to fill EPI FIFO. So you will have two different uDMA channels configured.

    The uDMA configuration needs to be setup for 8 words as the arbitration size for this to work so the SSI TX FIFO not overflowed.

    What you would need to do after configuring both interfaces is to then start the EPI first and use a non-blocking read to let it fill all 8 of it's FIFO entries. At this point, you start the SSI, and that should allow two burst requests of 4 bytes each to pull data from the EPI and into the SSI TX buffer. From there, the EPI should now start refilling it's FIFO. Then as long as the SDRAM data is accessed quicker and the FIFO is filled before the SSI TX is complete, the SSI should run at full speed.

    Not quite one command, but very close.

  • 0 in reply to Ali Naseri
    TI__Guru*** 134985 points

    Hi Ali,

    Had a bit more discussion regarding how the EPI works and the uDMA for EPI reading may not be needed but there is a little more handling involved. It should be mostly hands off though.

    For EPI you should be able to setup non-blocking reads by providing the start address, size, and count. The count can go up to 4095. What will happen then is the EPI will read data from the external device and fill the 8 layer deep FIFO. After the FIFO is full then it would stop until space is available, and resume at the next address read when there is space. So you wouldn't actually need the uDMA for this piece to have it be non-blocking.

    From the uDMA side, you can do up to 1024 bytes of transfer before you need to handle management of that.

    So there are two sets of EPI non-blocking read registers. By using ping-pong mode, the uDMA can transfer 1024 to SPI on the primary channel and then start working on the alternate channel with the second set of registers for the next 1024. You'd just need to service the uDMA interrupt every 1024 transfers to flip the DMA channel control and setup the next set of EPI non-blocking reads. So you'd set the EPI reads for 1024 bytes per read registers. The time to swap this over in the ISR shouldn't delay the SPI outputs at all.