FPGA -EPI interface problem in TM4C1294NCPDT?

Hello,

I am trying to access data from fpga to controller using EPI-HB16.Presently the interface is not working.I am attaching the code details of configuration and function calls.

1) In Main()

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

EPI_Init();
fpga_read();

2)

void EPI_Init(void)
{
// Enable EPI0.
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//Configure EPIO
EPIDividerSet(EPI0_BASE, 1);
EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
EPIConfigHB16Set(EPI0_BASE,(EPI_HB16_MODE_SRAM | EPI_HB16_WRWAIT_1 |EPI_HB16_RDWAIT_1 | EPI_HB16_WORD_ACCESS), 0);
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_BASE_C | EPI_ADDR_PER_SIZE_256B);////0xC0000000

EPIFIFOConfig(EPI0_BASE, EPI_FIFO_CONFIG_TX_EMPTY | EPI_FIFO_CONFIG_RX_1_4);

// Configure GPIO
GPIOPinConfigure(GPIO_PB3_EPI0S28); //RD
GPIOPinConfigure(GPIO_PP2_EPI0S29); //WR

GPIOPinConfigure(GPIO_PK0_EPI0S0); //D0
GPIOPinConfigure(GPIO_PK1_EPI0S1); //D1
GPIOPinConfigure(GPIO_PK2_EPI0S2); //D2
GPIOPinConfigure(GPIO_PK3_EPI0S3); //D3
GPIOPinConfigure(GPIO_PC7_EPI0S4); //D4
GPIOPinConfigure(GPIO_PC6_EPI0S5); //D5
GPIOPinConfigure(GPIO_PC5_EPI0S6); //D6
GPIOPinConfigure(GPIO_PC4_EPI0S7); //D7
GPIOPinConfigure(GPIO_PA6_EPI0S8); //D8
GPIOPinConfigure(GPIO_PA7_EPI0S9); //D9
GPIOPinConfigure(GPIO_PG1_EPI0S10); //D10
GPIOPinConfigure(GPIO_PG0_EPI0S11); //D11
GPIOPinConfigure(GPIO_PM3_EPI0S12); //D12
GPIOPinConfigure(GPIO_PM2_EPI0S13); //D13
GPIOPinConfigure(GPIO_PM1_EPI0S14); //D14
GPIOPinConfigure(GPIO_PM0_EPI0S15); //D15

GPIOPinConfigure(GPIO_PL0_EPI0S16); //A0
GPIOPinConfigure(GPIO_PL1_EPI0S17); //A1
GPIOPinConfigure(GPIO_PL2_EPI0S18); //A2
GPIOPinConfigure(GPIO_PL3_EPI0S19); //A3
GPIOPinConfigure(GPIO_PQ0_EPI0S20); //A4
GPIOPinConfigure(GPIO_PQ1_EPI0S21); //A5
GPIOPinConfigure(GPIO_PQ2_EPI0S22); //A6
GPIOPinConfigure(GPIO_PQ3_EPI0S23); //A7
GPIOPinConfigure(GPIO_PK7_EPI0S24); //A8
GPIOPinConfigure(GPIO_PK6_EPI0S25); //A9
GPIOPinConfigure(GPIO_PL4_EPI0S26); //A10
GPIOPinConfigure(GPIO_PB2_EPI0S27); //A11

GPIOPinConfigure(GPIO_PP3_EPI0S30); //CHIP SELECT
GPIOPinConfigure(GPIO_PK5_EPI0S31); //CLK
GPIOPinConfigure(GPIO_PK4_EPI0S32); //IRDY
GPIOPinConfigure(GPIO_PN5_EPI0S35); //CRE

GPIOPinTypeEPI(GPIO_PORTA_BASE, 0xC0);
GPIOPinTypeEPI(GPIO_PORTB_BASE, 0x0C);
GPIOPinTypeEPI(GPIO_PORTC_BASE, 0xF0);
GPIOPinTypeEPI(GPIO_PORTG_BASE, 0x03);
GPIOPinTypeEPI(GPIO_PORTK_BASE, 0xFF);
GPIOPinTypeEPI(GPIO_PORTL_BASE, 0x1F);
GPIOPinTypeEPI(GPIO_PORTM_BASE, 0x0F);
GPIOPinTypeEPI(GPIO_PORTN_BASE, 0x20);
GPIOPinTypeEPI(GPIO_PORTP_BASE, 0x0C);
GPIOPinTypeEPI(GPIO_PORTQ_BASE, 0x0F);

GPIOPadConfigSet (GPIO_PORTA_BASE, 0xC0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTB_BASE, 0x0C, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTC_BASE, 0xF0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTG_BASE, 0x03, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTK_BASE, 0xFF, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTL_BASE, 0x1F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTM_BASE, 0x0F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTN_BASE, 0x20, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTP_BASE, 0x0C, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTQ_BASE, 0x0F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIODirModeSet (GPIO_PORTA_BASE, 0xC0, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTB_BASE, 0x0C, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTC_BASE, 0xF0, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTG_BASE, 0x03, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTK_BASE, 0xFF, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTL_BASE, 0x1F, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTM_BASE, 0x0F, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTN_BASE, 0x20, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTP_BASE, 0x0C, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTQ_BASE, 0x0F, GPIO_DIR_MODE_HW);

}

void fpga_read()
{

#if 0
char *temp;

datasram = ( char *)malloc(1456*sizeof( char));
temp = datasram;

g_pusEPIFPGA = (char*)0xC0000000;

for(i = 0;i<1440;i++)
{
*datasram = g_pusEPIFPGA[index];
*datasram++;
}

datasram = temp;

free(datasram);
#endif

unsigned char *cptr = (unsigned char *)0xC0000000;
cval = *cptr;

// cval = *cptr;

cptr = (unsigned char *)0xC0000001;
cval = *cptr;

cptr = (unsigned char *)0xC0000002;
cval = *cptr;

cptr = (unsigned char *)0xC000000;
cval = *cptr;

cptr = (unsigned char *)0xC0000003;
cval = *cptr;

/* cptr = (unsigned char *)0xC0000004;
cval = *cptr;

cptr = (unsigned char *)0xC0000001;
cval = *cptr; */
}

Intially we are tryiing with out interrupts,weather interrupts are must,waether the haeder "inc/tm4c1294ncpdt is needed".

Any suggestions or idea plese replay.

Advance thanking .

Regards,

Krishnan