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Original question:

TMS570LS1224: DCAN, why there are so many message boxes? why we need 64?

TMS570LS1224: DCAN DMA

Long Nguyen89978
Prodigy 50 points
Part Number: TMS570LS1224

Hi support,

I am writing driver for DCAN module, and I am not sure which approach would be the best.

The ultimate goal is to receive all messages on the bus without message loss, but avoiding using interrupt.

I am thinking of using DMA to directly move message once received, however according to the manual, message RAM can only access directly in debug or test (RDA) mode.

Can you please give some advice on this? A simple DMA example would be greate.

Many thanks.

P

  • 0
    TI__Guru**** 192666 points

    Hello,

    The CAN message RAM can be directly access by CPU or DMA in test mode. During normal operation direct access has to be avoided. During normal operation, data consistency of the message objects is guaranteed by using the interface registers IF1 and IF2.

    The IF3 can be configured to automatically receive control and data from the Message RAM when a message object has been updated after reception of a CAN message. The CPU does not need to initiate the transfer from Message RAM to IF3 Register set.

    DMA is configured to transfer data from IFx data register to CPU SRAM or EMIF memory.