TMS570LC4357: Hardware support for Cache invalidation in write back doesn't flush the cache

Zakaria Nakrachi

Part Number: TMS570LC4357

Hi everyone,

I need to invalidate the cache between each process switch, in write-trough mode the hardware these instruction seems to do the job correctly :

  mov r0, #0
  # invalidate entire data cache
  MCR p15, #0, R0, c15, c5, #0
  DSB

  # invalidate entire instruction cache
  MCR p15, #0, R0, c7, c5, #0
  # ensures that all subsequent instruction fetches
  ISB

When in write-back mode, the cache is not flushed and we have a coherency problem. the only way we can get it to work with the write-back is to do a line-by-line invalidation of the cache which takes more time.

I just wanted to confirm if there is a single instruction to invalidate and flush the cache, or we absolutely need to go with the line-by-line approach when in write back mode ?

Thank you

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 196776 points

Hello,

You can invalidate the whole instruction cache, or invalidate the cache line by line. After invalidation, please re-enable the instruction cache.

I remember that c7, c5, #1 is used for line-by-line invalidation. Please check ARM TRM to get more information.

0 Zakaria Nakrachi over 5 years ago in reply to QJ Wang

Prodigy 130 points

Thank you for your quick reply,

I think my question wasn't clear, in fact I have implemented both approaches,

To invalidate the Data cache when using write-back policy we are using this

InvalidateL1DataCache:
    stmfd	sp!, {r4-r5, r7, r9-r11, lr}
    DMB									@ ensure ordering with previous memory accesses
    MRC		p15, 1, r0, c0, c0, 1		@ read clidr
    MOV		r3, r0, lsr #23				@ move LoC into position . [Level of Coherence(LoC)]
    ANDS	r3, r3, #7 << 1				@ extract LoC*2 from clidr . [Level of Coherence(LoC)]
    BEQ		invalFinished				@ if loc is 0, then no need to clean
    MOV		r10, #0						@ start clean at cache level 0
invalLevels:
    ADD		r2, r10, r10, lsr #1		@ work out 3x current cache level
    MOV		r1, r0, lsr r2				@ extract cache type bits from clidr
    AND		r1, r1, #7					@ mask of the bits for current cache only
    CMP		r1, #2						@ see what cache we have at this level
    BLT		invalSkip					@ skip if no cache, or just i-cache
    MRC		p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
    ISB									@ isb to sych the new cssr&csidr

    MRC		p15, 1, r1, c0, c0, 0		@ read the new csidr . The cache size ID register
    AND	r2, r1, #7						@ extract the length of the cache lines
    ADD	r2, r2, #4						@ add 4 (line length offset)
    MOVW	r4, #0x3ff
    ANDS	r4, r4, r1, lsr #3			@ find maximum number on the way size
    CLZ		r5, r4						@ find bit position of way size increment
    MOVW	r7, #0x7fff
    ANDS	r7, r7, r1, lsr #13			@ extract max number of the index size
invalLoop1:
    mov	r9, r7							@ create working copy of max index
invalLoop2:
    ORR		r11, r10, r4, lsl r5		@ factor way and cache number into r11
    ORR		r11, r11, r9, lsl r2		@ factor index number into r11

    MCR		p15, 0, r11, c7, c14, 2		@ invalidate line
    SUBS	r9, r9, #1					@ decrement the index
    BGE		invalLoop2
    SUBS	r4, r4, #1					@ decrement the way
    BGE		invalLoop1
invalSkip:
    ADD		r10, r10, #2				@ increment cache number
    CMP		r3, r10
    BGT		invalLevels
invalFinished:
    MOV		r10, #0						@ swith back to cache level 0
    MCR		p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
    DSB		
    ISB
    ldmfd	sp!, {r4-r5, r7, r9-r11, lr}
    bx	lr
InvalidateL1DataCache_End:

it slows down our process switch, I was wondering if we have one instruction to invalidate and flush the whole data cache, I've looked in ARM and TI's documentation but I wasn't able to find it.

Thank you

0 QJ Wang over 5 years ago in reply to Zakaria Nakrachi

TI__Guru**** 196776 points

MCR CP15, 0, 0, C7, C5, #0 --> is to invalidate the whole ICache.

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TMS570LC4357: Hardware support for Cache invalidation in write back doesn't flush the cache