TMS570LC4357: ESM 1.26 Error by writing to ECC SRAM of Level 2 SRAM?

Hello,

(Q1) Is it possible to force an ESM Group 1 Error Channel 26 (1.26) by writing to ECC SRAM with ERR_WR_EN = 1?

>> Please see the implementation of the 1-bit error forcing test included in the safeTI diagnostics library for TMS570LC4357.

(Q2) Isn't the ESM 1.26 really including read-modify-write accesses as like as an ESM 3.3 does?

>> ECC checking is done on a read from the SRAM. This read can be caused by the CPU explicitly reading from the SRAM location, or by an implicit read caused by a R-M-W operation by the CPU writing to the SRAM with data size < 64 bits.

Hi, Sunil,

Thank you for your answer to my questions.

In fact i did a typo which may has been misleading.

Let me precise the focus of my questions:

There are two procedures to test Level 2 SRAM Wrapper (L2RAMW); these procedures are both parts of RAM12 "Software Test of SRAM Wrapper Address Decode and ECC":

(procedure 1): Stimulating DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC, and RAMADDRDEC_VECT and
carrying out the procedure sketched in section 8.2.6 of the TRM spnu536a.

(procedure 2): Writing to ECC SRAM space after enabling those write accesses by setting RAMCTRL.ECC_WR_EN = 1[not ERR_WR_EN].

So my questions are on procedure 2:

(Q1) Bits RAMERRSTATUS.{22,21,20,19,12,,11,10,4} are not touched by procedure 2, right?

(Q2) Are RAMERRSTATUS.{RMWDE,CPUWDE} connected to an ESM Group 3 Channel 3 (3.3) error?

(Q3) Is RAMERRSTATUS.CPUWE connected to an ESM Group 1 Channel 26 (1.26) error?

(Q4) Are there no read-modify-write single bit errors (from CPU or from non-CPU bus masters)? Neither in RAMERRSTATUS nor signaled by (ESM)?
If so, does that mean, that RMW single bit errors are corrected quietly?

Thank you supporting us! Enjoy the week!

Stephan

Hello Stephan,

The procedure for testing the diagnostic SECDED mechanism within the L2RAMW is described in the reference manual SPNU563a in section 8.6.2 on page 392. You can use the method described in this section to generate all 1-bit and 2-bit errors detected by this SECDED logic.

Dear Sunil,

Currently i suppose that not an ESM 1.26 error is issued but an ESM 2.7 following the DRSE bit in register [RAMERRSTATUS].

We worked out a RTL schematic for write/read-modify-writes accesses to L2RAM.
Would you be so kind as to review the following drawing and tell us whether it is functionally correct or not:

4617.SAF-MCU-xxxx_RAM12_Diagnostics.vsdx.pdf

Thank you in advance

Stephan

Hi Stephan,

Unfortunately, I don't have the ability to confirm whether the RTL implementation matches the drawing or not.

Regards, Sunil

Just for clarifcation.

My current understanding is that the proposed RTL schematic has to be extended in that way that a MUX is missing on the data path;
that MUX has to be controlled by [RMMTEST].TEST_MODE as the MUX in the ECC path already is.

Stephan