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TMS570LC4357: SRAM ECC ERROR FORCING 1BIT and 2BIT generates exception

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi

I am facing a issue when using safety library to execute SRAM_ECC_ERROR_FORCING_2BIT,SRAM_ECC_ERROR_FORCING_1BIT selft test.

This issue is only observed when application is combined with a boot loader application.

But if application run standalone then issue is not observed.

I need help to resolve this issue.

retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);
/* Run 1Bit ECC test on sRAM */
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &failInfoTCMRAM);

below is application link file configuration.

MEMORY
{
/* These configuration settings are required for all SafeRTOS based
* applications.
* If the whole build is using ARM mode then VECTORS length can be 0x20.
* When using thumb mode, 0x80 is required to accommodate the interwork
* code. */

VECTORS (X) : origin=0x00200000 length=0x00000080 vfill = 0xffffffff
KERN_FUNC (RX) : origin=0x00200080 length=0x0000ff80 vfill = 0xffffffff
FLASH0 (RX) : origin=0x00210000 length=0x001D0000 vfill = 0xffffffff
STACKS (RW) : origin=0x08000000 length=0x00003000
KERN_DATA (RW) : origin=0x08003000 length=0x00002000
RAM (RW) : origin=0x08005000 length=0x0007B000


ECC_VEC (R) : origin=0xf0400000 length=0x10 ECC={ input_range=VECTORS }
ECC_KERN (R) : origin=0xf0400000 + 0x10 length=0x1ff0 ECC={input_range=KERN_FUNC}
ECC_FLA0 (R) : origin=0xf0400000 + 0x10 + 0x1ff0 length=0x2e000 ECC={input_range=FLASH0}

}


ECC {
algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
hamming_mask = R4 /* Use R4/R5 build in Mask */
parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
}

/*----------------------------------------------------------------------------*/
/* Section Configuration */

SECTIONS
{
/* These configuration settings are required for all SafeRTOS based
* applications. */

/* The following symbols need to be exported:
*
* lnkKernelFuncStartAddr - the start of the Flash memory section used during runtime.
*
* IMPORTANT NOTE: lnkKernelFuncStartAddr can be relocated (e.g. when a
* bootloader is used), but it must be aligned according to its size
* (rounded up to the next power of 2), otherwise the MPU will be
* configured incorrectly.
*
* lnkEndFlashAddress - the end of the Flash memory section used during runtime.
*
* lnkKernelFuncStartAddr - the start address of the Flash block containing
* the interrupt vector table and the kernel functions.
* NOTE: This should be aligned according to the section size, i.e. 0x8000.
*
* lnkKernelFuncEndAddr - the end address of the Flash block containing
* the interrupt vector table and the kernel functions.
*
* lnkKernelDataStartAddr - the start address of the RAM block containing
* the system stacks and the kernel data.
*
* lnkKernelDataEndAddr - the end address of the RAM block containing
* the system stacks and the kernel data.
*/

/* On this demo application, the kernel functions section is placed at the
* start of the Flash memory; this will not be the case if the application is relocated. */
.intvecs palign(32), START( lnkStartFlashAddress ),START( lnkKernelFuncStartAddr )
fill =0xffffffff {} > VECTORS

.kernel_function END( lnkKernelFuncEndAddr ) :
{
*(KERNEL_FUNCTION)
} > KERN_FUNC

.unpriv_flash palign(32), END( lnkEndFlashAddress ) :
{
*(.text)
*(.const)
} > FLASH0

.cinit align(32) : {} > FLASH0
.pinit align(32) : {} > FLASH0

STACK_DATA START( lnkKernelDataStartAddr ) : {} > STACKS
KERNEL_DATA END( lnkKernelDataEndAddr ) : {} > KERN_DATA

.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM
LOG_DATA : > RAM //LOG
PROFILE_DATA : > RAM //PROFILE
/* These configuration settings are for the SafeRTOS TMS570LC43x FPU demonstration
* project. They are included as a demonstration of how task data can be
* grouped together into known locations, therefore enabling MPU regions to
* be defined. */

__idle_hook_data__
: START( lnkIdleTaskDataStartAddr )
{} > RAM palign( 0x20 )

}