• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 510 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: Problem when using the MCU internal I2C and the MibADC1 modules

Chuck Wong
Genius 3950 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: TCA6424A,

Hello there,

In our design we are using the TMS570LS3137 MCU's internal I2C and the MibADC1 modules. By design they are completely independent, meaning that device signals are not crosslinked between those two modules. The I2C module is configured to work with a 400 kHz device (SCLK verified), namely an TI I/O expander P/N TCA6424A, while the MibADC1 module is configured to acquire 12 analog channels with a sampling time of 2us per channel.

Prior enabling MibADC1, the 24-bit I2C I/O expander was configured with 2 input ports and one output port. The configuration registers values read back confirms the correct configuration, and predefined input ports states are correctly read back too. Now with the I2C NOT operating, the MibADC1 is launched and all channels values are correctly batch-acquired every 50ms.

The MibADC1 acquisition mechanism is without software intervention and configured as follow:

  1. RTI compare event 2 to start the MibADC1 HW sampling sequence (every 50ms)
  2. When sampling done (12x2us=24us), a preprogrammed DMA is triggered and channel data are transferred to software RAM
  3. When DMA transfer was done, an software IRQ is called to convert channel binary data to analog data

However, starting from the moment the I2C module is instructed to read or write (also every 50ms), all MibADC1 channels readings now contain the very same but wrong 24-bit binary value, and this value does not vary, not even one single bit, until when the I2C bus is having problem (with the Bus Busy=1 and cannot release Master Mode=1 ... we don't know why yet), typically within a second or two, then the MibADC1 restarts operating correctly with correct channel voltages (I2C bus won't work from this point on).

Anyone can tell me where to look please?

Thanks.

  • 0
    TI__Guru**** 197356 points

    Hello Chuck,

    The I2C module and ADC module are two independent modules.

    Is RTI compare event also used for I2C read/write? Is the wrong ADC data related to I2C data (R or W)? Can you share your code for ADC reading and I2C reading/writing?

  • 0 in reply to QJ Wang
    Genius 3950 points

    Good day QJ,

    I've just PM the source file to you.

    Thank you very much for your time.

  • 0 in reply to Chuck Wong
    Genius 3950 points

    Hi QJ,

    Well, I've found the problem for the duality between the I2C module and the MibADC1 module, their setup details are in my first post above.

    Since I'm using the DMA to transfer data from the MibADC1 Group2 FIFO buffer to the SW RAM, while both modules are independent from one the other inside the MCU, I believe that it is incorrect to state that their operations in the SW standpoint are independent, for the very reason that the I2C Transmit DMA source is sharing the same request line as the MibADC1 Group2 DMA source, which is DMAREQ[11] in this case.

    As a consequence, when the I2C is working correctly, the MibADC1G2 operation degrades since this latter was also programmed to use DMAREQ[11]. After the I2C ceased to operate correctly, the MibADC1G2 comes back to life.

    That been said, my couple of workdays productivity lost was caused by the fact that I haven't been able to guess to the point that both I2CDMACR.TXDMAEN and I2CDMACR.RXDMAEN were default to 1 (enabled) with this TMS570LS3137 MCU (page 1603 of the TRM spnu499c).

    How could this be?

    Could you please explain the logic behind this default setting and not been clearly indicated?

    Any other module has their DMA default to ON?

    Or maybe I've missed something more important than that?

    Best regards.

  • 0 in reply to Chuck Wong
    Genius 3950 points

    QJ, 

    For your information, the I2C read/write was not programmed in the SW to use the RTI at all.

    Thanks.

  • 0 in reply to Chuck Wong
    Expert 1285 points

    Hi Chuck,

    Thanks for finding and sharing this critical piece of info. Nice detective work! Hope there is no other instances like this!

    Joe

  • 0 in reply to Joe Josn
    TI__Guru**** 197356 points

    Hello Chuck,

    Yes, I2C DMA transmit/receive events are enabled by default. The DMA in most of modules (SCI, SPI, etc) is disabled by default.

  • 0 in reply to QJ Wang
    Genius 3950 points

    Hi QJ,

    Any rational from the design team as on why those two events are DMA enabled?

    There must be something as even when enabled, the user still needs to configured the corresponding DMA channel in order to make it worked, and I can't see this requirement anywhere. 

    Thanks.