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TMS570LS3137: Using RTI event0 to HW trigger MibADC1 Group2 conversion

Chuck Wong
Genius 3940 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hello there,

In our project we are using RTI compare block 0 as HW source to trig the MibADC1 Group2 conversion every 50 ms, and everything is going fine when the associated RTI compare block 0 interrupt is enabled, within which ISR the ONLY instruction "RTIINTFLAG &= 0x00000001;" is used to reset the event0 interrupt flag in order to prepare for the next one in 50ms. This cycle repeats continuously, which confirms that the RTI was correctly programmed and the MibADC1 Group2 is converting every time.

However, if the interrupt generation from the RTI compare block 0 was disabled (by clearing the SETINT0 bit of the RTISETINTENA register), because we don't need this SW interrupt overhead, and thinking that the internal HW trigger would continue to trig the MibADC1 Group2 conversion. But it doesn't because no more conversion are performed.

Our question is: how to NOT generate RTI compare block 0 interrupt while keeping the cyclic HW trigger active every 50 ms?

Many thanks,

Chuck.

  • 0
    TI__Mastermind 49120 points

    Hi Chuck,

    The RTI module supports an automatic clear of the compare match flag. You can use this to periodically trigger the ADC without having to service the RTI compare match interrupt using the CPU.

    See this thread that answers the same question:

    https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/685763

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Genius 3940 points

    Hi Sunil,

    Thanks for the link. However, when I clear the bit INTCLRENABLE0 in my code from 0x5 (default) to 0x0, the MibADC1 doesn't get triggered at all:

    RTICOMP0 = 50;
RTIUDCP0 = 50; 
RTICOMPCTRL_bit.COMPSEL0 = 0;
RTISETINTENA_bit.SETINT0 = 1;

RTIINTCLRENABLE_bit.INTCLRENABLE0 = 0x0;

    Anything that I forgot?

    Thanks.

  • 0 in reply to Chuck Wong
    Genius 3940 points

    Just to clarify, the above code is executed only once during initialization, and the RTIINTCLRENABLE register was configured correctly with value of 0x05050500 shown in the debugger for the rest of the session, so it does keep the desired value.

    In order to have the RTI compare 0 event0 to trig the internal MibADC1 cyclically, I have to enable VIM INT #2 and have the RTIINTFLAG register cleared manually for now.

  • 0 in reply to Chuck Wong
    TI__Mastermind 49120 points

    Hi Chuck,

    You should not need to enable the interrupt in VIM. I will send you an example configuration routine later today.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Genius 3940 points

    Thanks Sunil,

    Just want to mention that I'm not using HalCoGen, and I'm on IAR EWARM IDE.

    Thanks.

  • 0 in reply to Chuck Wong
    Genius 3940 points

    Hi Sunil,

    So I've found my problem for using the internal RTI compare 0 trigger to start MibADC reading, and without using the VIM #2 ISR.

    The register to enable auto-clear would have to be used in tandem with the RTICOMP0CLR register. Therefore, is I want the RTI INT to be cleared following the first compare match at 50 ms, let say, I would have to configure the RTICOMP0CLR also.

    RTICOMP0 = 50;                  
RTIUDCP0 = 50;                  
RTICOMPCTRL_bit.COMPSEL0 = 0;   
RTISETINTENA_bit.SETINT0 = 1;   

RTIINTCLRENABLE_bit.INTCLRENABLE0 = 0xA;
RTICOMP0CLR = 51;

    So with the above code, the INT clearing operation would happen at 51 ms, 101 ms, 151 ms and so on. Now I don't have to enable VIM #2 ISR.

    Thank you for helping.

  • 0 in reply to Chuck Wong
    TI__Mastermind 49120 points

    Thanks for the confirmation.

    Regards,

    Sunil