• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 286 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28035: Questions about EPwm submodule Trip-Zone

Green Deng
Expert 4490 points
Part Number: TMS320F28035

Dear team:

My client wants to clear the TZCLR[CBC] bit in the TZ interrupt, but it has no effect (there is indeed an entry interrupt). It can only be cleared when CTR=zero.

He made some modifications on the basis of routines. The following are some of his code settings:

Fullscreen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EALLOW;
// Define an event (DCAEVT1) based on TZ1 and TZ2
EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_COMP1OUT; // DCAL = Comparator 1 output
// EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAL_LOW; // DCAEVT2 = DCAL low(will become active as Comparator output goes low)
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
EPwm1Regs.TZSEL.bit.DCAEVT2 = 1;
EPwm1Regs.TZCTL.bit.TZA= TZ_FORCE_LO; // EPWM1A will go high
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE; // EPWM1B will go low
EPwm1Regs.TZEINT.bit.CBC = 1;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Will the above code cause the problem mentioned by the customer?

Best regards