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Original question:

TMS320F28374S: The maximum UART baud rate by the SCI peripherals

TMS320F280025C: Huge errors in SCI baud rates with 20 MHz crystal on F28002x launchpad

Asad Hameed
Intellectual 695 points
Part Number: TMS320F280025C
Other Parts Discussed in Thread: C2000WARE

I want to communicate TMS320F280025C with a single board computer that allows standard & high baud rated including:1200,2400,4800,9600,19200,38400,57600,115200,230400,460800,921600.I have done calculations on achievable baud rated on TMS320F280025C with 20 Mhz external crystal and having system clock of 100 MHz. The calculations shows high percentage error while trying to achieve 115200 or higher baud rates:

Baud Rate required LSPCLK(MHz) BRR Calculated Actual Baud Rate %error
1200 100 10418 1200 0
2400 100 5209 2399 0.041667
4800 100 2604 4798 0.041667
9600 100 1302 9593 0.072917
19200 100 651 19172 0.145833
38400 100 326 38226 0.453125
57600 100 217 57339 0.453125
115200 100 109 113636 1.357639
230400 100 54 227273 1.357205
460800 100 27 446429 3.118707
921600 100 14 833333 9.577582

The following formulas are used for calculating BRR & actual baud rate:

BRR = LSPCLK / (SCI Asynchronous Baud * 8) - 1
Actual Baud Rate= SCI Asynchronous Baud = LSPCLK / ((BRR + 1) *8)

I am looking forward to some expert opinion and possible solution to achieve high baud rate with low error while not compromising on main CPU clock i.e. 100 MHz.

  • 0
    TI__Mastermind 19795 points

    Hi Asad,

    Thanks for your question! Regarding this, as you noted, the higher the baud rate the more error due to less BRR granularity at the high-end of the baud spectrum.

    Currently, if the SYSCLK must be locked to 100MHz, there are only 2 modifiable variables: BRR and the LSPCLK.

    Therefore, if possible, I would suggest modifying the LSPCLK to allow for a low percent error at your desired baud rate.

    For example, with a SYSCLK of 100, a LSPCLK of 100 (divider = /1), and a BRR of 26, a baud rate of approximately 462963 can be achieved. This is about 0.47% off from the desired 460800 baud rate (which may be acceptable).

    Please also note that as with any high-speed communication that lacks a clock line, the oscillator tolerances of both sides of the communication become important and play a role in the error. Additionally, excellent noise isolation (of the communication lines) and high-quality board layout must be followed in order to prevent skew that would lead to high-error-rates.

    Regards,

    Vince

  • 0 in reply to Vince
    Intellectual 695 points

    Dear Vince,
          Thank you very much for a useful technical guidance. Meanwhile we are also considering SPI option. Your expert opinion in this regard will be useful. I understand that we can use SPI with DMA controller for direct communication between the single board computer (Jetson Nano) and TMS320F280025C. The expected outcomes of this approach are:
    1- Main CPU bandwidth will be available for other tasks. Minimum or no interaction from the main CPU should be required except for updating the data at its available time.
    2- Minimum communication errors due to synchronization clock & relatively low latency in communication.
    Kindly let me know if the above understanding is correct. Also let me know if there is any related literature besides technical reference manual that can help me understand DMA and SPI integration. At present I am looking into the example SPI projects in the C2000Ware repository to gain some understanding.

  • 0 in reply to Asad Hameed
    TI__Mastermind 19795 points

    Hi Asad,

    Glad I could be of help with the SCI! I have reached out to our SPI expert to provide some guidance regarding getting started with SPI, particularly with examples, interrupts, and DMA access.

    Regards,

    Vince

  • +1 in reply to Vince
    TI__Guru 55700 points

    Asad,

    You should be able to use SPI with DMA to achieve minimum CPU intervention. Please check below C2000Ware example

    Path       :        <C2000Ware>\driverlib\f28002x\examples\spi

    Example:   spi_ex4_loopback_dma

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 695 points

    Thank you very much for your feedback and example referral. The example is a good reference for basic setup. In our application the information exchange will be variable length and from different memory locations. I understand this will need some protocol over the basic SPI communication. This protocol could have fields specifying  read/write, start address, length etc. This means that DMA will need to be configured each time by the main CPU to perform required transfers. So initial interrupt might need to be processed by the main CPU and then subsequent transfers to be performed by the DMA. Is there a better way to do this?. Can you refer any open source protocol to serve as design guidelines?.

  • 0 in reply to Asad Hameed
    TI__Guru 55700 points

    Asad,

    I unfortunately don't have specific example to share for the usecase you are mentioning. DMA has 6 channels, if you have different memory locations and variable lengths you can consider using each of these 6 channels to your advantage. But, if you prefer to use one DMA channel then you need to use CPU to change the DMA configurations. There is no other option.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 695 points

    Please let me know if the following understanding is correct: With TMS320F28002x acting as a SPI slave device I can configure multiple DMA channels for different memory locations. Upon receiving SPI command from master the CPU needs to service the FIFO interrupt to check and trigger appropriate DMA channel for reading/writing to the related memory location. This initial interrupt processing from the CPU is unavoidable?.

  • 0 in reply to Asad Hameed
    TI__Guru 55700 points

    Asad,

    Yes, SPI FIFO RX interrupt needs to be used to understand the command received and then decode the command to fire appropriate DMA channel. This part is unavoidable.

    Regards,

    Manoj