• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 358 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28075: Can TZCLR.bit.OST clear the one shot trip signal when PWM TBCTR counts to 0?

Howard Zou
Genius 12365 points
Part Number: TMS320F28075

Hi,

my customer says that when they clear the one shot trip signal with "EPWMxRegs.TZCLR.bit.OST=1", the duty cycle of the first PWM cycle may not be as expected.

If we could configure "EPWMxRegs.TZCLR.bit.OST=1" to take effect at TBCTR=0, like shadow registers, we could avoid such problem.

Do you have any idea how we could clear the one shot trip signal at the instance when TBCTR counts to 0?

  • +1
    TI__Mastermind 23480 points

    Hi Howard,

    Howard Zou said:
    Do you have any idea how we could clear the one shot trip signal at the instance when TBCTR counts to 0?

    One shot (OSHT) trip events do not have a clearing mechanism like Cycle by Cycle trip events where you can decide to clear on PRD or ZRO. One possible suggestion to implement something like this is to generate an interrupt when TBCTR = 0. Within the ISR for that interrupt you can set EPWMxRegs.TZCLR.bit.OST=1. 

    Best Regards,

    Marlyn