• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 81 subscribers
  • Views 198 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: Dual-core programming issue in standalone mode when RAM-Sharing is active between the cores.

Swathy Pillai
Prodigy 10 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hi,

So I am new to F28379d and I am trying out examples on launchpad for developing a program and I am facing the issue that when RAM sharing is active between 2 cores ,the cores aren't retaining the program after power reset.

The process I follow for programming the cores is:

Setting the configuration(i.e. choosing as per need RAM/FLASH/STANDALONE)  in properties for the project and  first debugging it to the core-1 after which I use connect target for core-2 and Load the program out file in the core 2 .After which I click resume for both cores individually to run both .

Here's a brief description of what I have tried out for your reference :- 

So, I was trying out Blinky_dc and RAM_management programs in examples for TMS320F28379d in c2000ware version 3_03 as well as 3_04. 

1) Blinky_dc program works fine in both debugging (CPU1- flash & CPU2-flash)  and standalone modes : - (CPU1 - standalone configuration and CPU2-flash mode). So the program is functional even in power reset case in standalone mode

2) Moving on to RAM_management program, I tried the same approach of CPU1-standalone and CPU2-flash mode but it fails on power reset  and I need to keep working in debug mode(CPU1-flash mode CPU2-flash mode )and thus use jtag to  program the cores every day for testing.

I need a solution to this so that both the cores can be functional after power reset even when ram sharing is active between the cores. Please do let me know the needed corrections for solving this issue.

  • 0
    TI__Guru** 109165 points

    Hi Swathy,

    Swathy Pillai said:
    I am facing the issue that when RAM sharing is active between 2 cores ,the cores aren't retaining the program after power reset.

    On this device all the RAMs are initialized on any reset which toggles XRSn pin so this is expected behavior. RAMs are volatile memory so content is not retain after power on reset. For that you need to use the FLASH which is non-volatile memory (like step 1 you are doing). RAM configuration is only for initial development where you have CCS connected and load the code via CCS and then run it.

    Regards,

    Vivek Singh 

  • 0 in reply to Vivek Singh
    Prodigy 10 points

    Hi Vivek

    As i explained I am using flash modes only .The cores are using global shared RAM's between each other but i programmed them both in Flash modes. The  core 2  in flash mode and flash standalone mode in core1 so both are basically  using flash linker cmd files and not  RAM files. What should i do if it fails in this case. Was the method to program the cores wrong then or is there any other way ?

  • 0 in reply to Swathy Pillai
    TI__Guru** 109165 points

    Sorry, I misunderstood the issue. So basically if you load the code via CCS then it works fine but if you power cycle the board then it does not work. Since this example is about RAM management, it may be using RAM for code loading (I see isr.cmd file which is loading part of code into RAM) hence you are seeing this issue. It has nothing to do with RAM sharing. 

    Regards,

    Vivek Singh