TMS320F280049: Nested Interrupt on TMS320F280049

Rishabh,

I will refer to this wiki article to make sure the steps are being followed under the 1st nesting example.  You will see in step 3 there is mention of a 1 cycle delay between clearing the PIEACK and clearing the INTM bit, please make sure this is observed. https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

If there is still an issue after looking at the above, I would suggest you to post the ISR handler in question  as well as the interrupts that are being nested/active so we can evaluate the nesting code.  If there are other interrupts enabled that are in a higher priority group it would be possible those would get serviced 1st even if they came in later.

Best,

Matthew