TMS320F28386D: External interrupt can trigger CPU1 only

Henry Teng

Part Number: TMS320F28386D

Hi, there.

My requirement is to trigger DMA Channel 1 of CPU1 and CPU2 both by an external interrupt. The external interrupt source should be a single one GPIO, for example, GPIO 104. Please refer my topology like below:

In CPU1, I checked the code worked like:

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// Step 1 : assign XINT1 from some external input
GPIO_SetupXINT1Gpio(104);
// Step 2 : configure polarity
XintRegs.XINT1CR.bit.POLARITY = 1; // Rising edge interrupt
XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1
// Step 3 : assign routine
PieVectTable.DMA_CH1_INT = &DMA_CH1_isr; // assigned routine
// Step 4 : activate dma channel
// Ignore some other DMA CH1 config
....
DmaRegs.CH1.MODE.bit.CHINTE = 1;
PieCtrlRegs.PIEIER7.bit.INTx1 = 1;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

// Step 1 : assign XINT1 from some external input
GPIO_SetupXINT1Gpio(104);

// Step 2 : configure polarity
XintRegs.XINT1CR.bit.POLARITY = 1; // Rising edge interrupt
XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1

// Step 3 : assign routine
PieVectTable.DMA_CH1_INT = &DMA_CH1_isr; // assigned routine

// Step 4 : activate dma channel
// Ignore some other DMA CH1 config
....
DmaRegs.CH1.MODE.bit.CHINTE = 1;
PieCtrlRegs.PIEIER7.bit.INTx1 = 1;

In CPU2, Step 2 ~ 4 are coded. Step 1 seems not available in CPU2 (doesn't make sure of this).

I've checked DMA CH1 in CPU1 working fine, but the one in CPU2 didn't work. Could you please help this? What else should I take care of?

Regards,

Henry

over 3 years ago

0 Veena Kamath over 3 years ago

TI__Mastermind 32385 points

Hi Henry,

The GPIO and XBAR settings can be done only by CPU1 core. But the XintRegs can be configured on both the cores independently.

Have you configured the DMA trigger source as XINT1 in both CPU1 and CPU2 code?

Regards,

Veena

0 Henry Teng over 3 years ago in reply to Veena Kamath

Intellectual 515 points

Hi Veena,

Did you mean DmaClaSrcSelRegs.DMACHSRCSEL1? This one has been set to 29.

0 Veena Kamath over 3 years ago in reply to Henry Teng

TI__Mastermind 32385 points

Yes, I meant the DMACHSRCSEL registers. Is that configured on both the cores?

Regards,

Veena

0 Henry Teng over 3 years ago in reply to Veena Kamath

Intellectual 515 points

Yes, DMACHSRCSEL setting is checked. DMACHSRCSEL1.CH1 is set to 29 too in CPU2.

0 Henry Teng over 3 years ago in reply to Henry Teng

Intellectual 515 points

May I ask DMA CH1 in CPU1 and DMA CH1 in CPU2 are individual unit in each CPU? I make sure setting DMACHSRCSEL register is executed and DMA CH1 Mode, Control Registers is, too, due to those executions are put in one function and that function does run. But I can't read out both Mode and Control Registers (Both show "0")

Regards,

Henry

0 Veena Kamath over 3 years ago in reply to Henry Teng

TI__Mastermind 32385 points

Hi Henry,

Yes, these are dedicated DMAs for each of the CPU subsystems.

Have you used EALLOW before setting the control registers. Most of the DMA control registers are EALLOW protected.

Regards,

Veena

0 Henry Teng over 3 years ago in reply to Veena Kamath

Intellectual 515 points

I make sure of that Mode and Control Registers are both set between EALLOW and EDIS, DMACHSRCSEL as well. My code is like:

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void DMACH1Config(volatile Uint16 *DMA_Source, volatile Uint16 *DMA_Dest, Uint16 wordLen, Uint16 TriggerSource)
{
    Uint16 tsize = wordLen % 32 ? (wordLen/32 + 1) : wordLen/32;
    Uint16 bsize = wordLen / tsize;
    EALLOW;
    // Disable DMA channel
    DmaRegs.CH1.CONTROL.bit.RUN = 0;
    // Configure DMA Channel 1 (32-bit datasize)
    // Set up SOURCE address:
    DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;   // Point to beginning of source buffer
    DmaRegs.CH1.SRC_ADDR_SHADOW     = (Uint32)DMA_Source;
    // Set up DESTINATION address:
    DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;     // Point to beginning of destination buffer
    DmaRegs.CH1.DST_ADDR_SHADOW     = (Uint32)DMA_Dest;
    // Set up BURST registers:
    DmaRegs.CH1.BURST_SIZE.all = bsize-1;               // Number of words (X-1) transferred in a burst
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void DMACH1Config(volatile Uint16 *DMA_Source, volatile Uint16 *DMA_Dest, Uint16 wordLen, Uint16 TriggerSource)
{
    Uint16 tsize = wordLen % 32 ? (wordLen/32 + 1) : wordLen/32;
	Uint16 bsize = wordLen / tsize;

	EALLOW;

	// Disable DMA channel
	DmaRegs.CH1.CONTROL.bit.RUN = 0;

	// Configure DMA Channel 1 (32-bit datasize)
	// Set up SOURCE address:
	DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
	DmaRegs.CH1.SRC_ADDR_SHADOW		= (Uint32)DMA_Source;

	// Set up DESTINATION address:
	DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;		// Point to beginning of destination buffer
	DmaRegs.CH1.DST_ADDR_SHADOW		= (Uint32)DMA_Dest;

	// Set up BURST registers:
	DmaRegs.CH1.BURST_SIZE.all = bsize-1;				// Number of words (X-1) transferred in a burst
	DmaRegs.CH1.SRC_BURST_STEP = 2;						// Increment source addr between each word transferred
	DmaRegs.CH1.DST_BURST_STEP = 2;						// Increment dest addr between each word transferred

	// Set up TRANSFER registers:
	DmaRegs.CH1.TRANSFER_SIZE = tsize-1;				// Number of bursts (X-1) per transfer, DMA interrupt will occur after completed transfer
	DmaRegs.CH1.SRC_TRANSFER_STEP = 2;					// TRANSFER_STEP is ignored when WRAP occurs
	DmaRegs.CH1.DST_TRANSFER_STEP = 2;					// TRANSFER_STEP is ignored when WRAP occurs

	// Set up WRAP registers:
	DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;					// Wrap source address after N bursts
	DmaRegs.CH1.SRC_WRAP_STEP = 0;						// Step for source wrap

	DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;					// Wrap destination address after N bursts
	DmaRegs.CH1.DST_WRAP_STEP = 0;						// Step for destination wrap

	DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = TriggerSource;

	// Set up MODE Register:
	DmaRegs.CH1.MODE.bit.PERINTSEL	= 1;				// Should be hard coded to channel, above now selects source, 36:EPWM1.SOCA
	DmaRegs.CH1.MODE.bit.PERINTE	= PERINT_ENABLE;	// Peripheral interrupt enable
	DmaRegs.CH1.MODE.bit.ONESHOT	= ONESHOT_ENABLE;	// Oneshot enable
	DmaRegs.CH1.MODE.bit.CONTINUOUS	= CONT_ENABLE;		// Continous enable
	DmaRegs.CH1.MODE.bit.OVRINTE	= OVRFLOW_DISABLE;	// Enable/disable the overflow interrupt
	DmaRegs.CH1.MODE.bit.DATASIZE	= THIRTYTWO_BIT;	// 16-bit/32-bit data size transfers
	DmaRegs.CH1.MODE.bit.CHINTMODE	= CHINT_END;		// Generate interrupt to CPU at beginning/end of transfer
	DmaRegs.CH1.MODE.bit.CHINTE		= CHINT_ENABLE;

	// Clear any spurious flags:
	DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;				// Clear any spurious interrupt flags
	DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;					// Clear any spurious sync error flags

	// Initialize PIE vector for CPU interrupt:
	PieCtrlRegs.PIEIER7.bit.INTx1 = 1;

	// This function starts DMA Channel 1.
	DmaRegs.CH1.CONTROL.bit.RUN = 1;

	EDIS;

This part is just the same as code in CPU1. But it works fine in CPU1.

Additionally, the register of trigger source was set correctly. Did anything else should be noticed?

+1 Veena Kamath over 3 years ago in reply to Henry Teng

TI__Mastermind 32385 points

HI Henry,

Have you enabled the DMA peripheral clock on CPU2? Note that this should be set by CPU2

CpuSysRegs.PCLKCR0.bit.DMA = 1;

This is done as part of InitPeripheralClocks (also called in InitSysCtrl)

Regards,

Veena

0 Henry Teng over 3 years ago in reply to Veena Kamath

Intellectual 515 points

Haven't checked this register yet! I'll check this and report it.

0 Henry Teng over 3 years ago in reply to Veena Kamath

Intellectual 515 points

Thank you. It works! I did ignore this essential setting.

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TMS320F28386D: External interrupt can trigger CPU1 only