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Dear Champs,
I am asking this for our customer.
In the past, if we use EPWM1 as master to generate SYNCOUT and use EPWM2 to get SYNCI.
In F28004x TRM, 18.4.3.3 Time-Base Counter Synchronization,
it says
The delay from internal master module to slave modules is given by:
– if ( TBCLK = EPWMCLK): 2 x EPWMCLK
– if ( TBCLK < EPWMCLK): 1 x TBCLK
That is, if TBCLK = EPWMCLK, there is 2 clock cycle delay so that the EPWM2 TBPHS = 2 should be set if the sync from EPWM1 is generated at counter = 0.
However, on F28003x TRM 20.4.3.3 Time-Base Counter Synchronization, I don't see such description and I am aware that the sync scheme is enhanced on F28003x and F28002x.
Would you please confirm this TBPHS = 2 is not longer needed on F28002x/F28003x?
That is, the user just keeps TBPHS = 0 by default in EPWM slave.
Wayne Huang
The delay is still applicable.
I did TBCLK = EPWMCLK/8
So I expected a 1 CLOCK delay.
I set the phase between 1 and 2 to 300 and this is what I got:
As you can see the difference is 299 (1 cycle)
