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In SPRUG04A -- the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module (Rev. A) user guide -- the synchronization delay from internal master module to slave module is given on page 27.
However, it appears that the delays presented assume that both the master and the slave modules are clocked at the same frequency; if this isn't the case it is not certain to which module -- the master or the slave -- the references to SYSCLKOUT and TBCLK refer.
What is the synchronization delay from internal master to slave for cases when the ePWM modules are not clocked at the same frequency? I tabluated a small number of results and observed that the synchronization delay goes negative (the slave output changes before the master output) when the master clock is signifcantly slower than that of the slave.
Since my measurements are subject to error, it would be greatly appreciated if TI could provide an accurate set of such synchronization latency tabulations. Of highest interest, is confirmation of the frequency realm in which the synchronization delay is negative.
For the following table, the slave module was always clocked at TBCLK_slave=SYSCLKOUT, (TBCTL:CLKDIV = 0, TBCTL:HSPCLKDIV = 0).
| Master CLKDIV | Master HSPCLKDIV | Master TBCLK | Slave TBCLK | Master to Slave Synchronization Delay |
| 1 | 1 | SYSCLKOUT/1 | SYSCLKOUT | 2 x SYSCLKOUT |
| 1 | 2 | SYSCLKOUT/2 | SYSCLKOUT | 1 x SYSCLKOUT |
| 1 | 4 | SYSCLKOUT/4 | SYSCLKOUT | -1 x SYSCLKOUT |
| 1 | 6 | SYSCLKOUT/6 | SYSCLKOUT | -1 x SYSCLKOUT |
| 1 | 10 | SYSCLKOUT/10 | SYSCLKOUT | -7 x SYSCLKOUT |
| 1 | 14 | SYSCLKOUT/14 | SYSCLKOUT | -11 x SYSCLKOUT |
Thank you for your help,
Mark
