• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 83 subscribers
  • Views 400 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280025C: CLB output routing

david goodin
Intellectual 390 points
Part Number: TMS320F280025C

From what I understand, the CLB output routing can go different places depending on the mux settings. In this case, I want to have an output from the CBL go to the "SYNC" input of a PWM so that I can reload the time base counter. The only path I see for that is going out to a GPIO (from CLB) and then tying that GPIO to the SYNC line of the PWM. 

I am, of course, short on free GPIO's The manual states something about the GPIO buffer usage regardless of the "MUX" setting for the physical pin. 

So...can I use a GPIO for this signal path when the physical pin related to that GPIO is used for something else? Say, PWM or SCIO?

David

  • 0
    TI__Genius 14171 points

    Hi David,

    Can you show me where in the documentation you are referring to? Let me transfer this to our GPIO expert

    Regards,

    Peter

  • 0 in reply to Peter Luong1
    TI__Mastermind 19795 points

    Hi David,

    Thanks for your question. From the GPIO side of things, if you are using the GPIO -AND- the CLB is using the Input/Output XBAR of that GPIO, then you will have a conflict. The question then becomes whether the CLB input-xbar is using the GPIO XBAR connection, or a separate connection. I will request Peter to look at it from that perspective now.

    Hi ,

    Can you provide to David whether the CLB xbar is tied to the GPIO xbar in any way? I am not familiar with the CLB architecture. The specific question here is whether the "CBL<-->EPWM SYNC input" connection uses the GPIO XBAR or MUX.

    [EDIT] NOTE: There will be maintenance to E2E for the next few days, so please expect delay in response. Apologies in advance for the inconvenience.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Genius 14171 points

    Thanks Vince for your input from the GPIO perspective.

    David,

    There is no direct connection from the CLB output to the ePWM SYNC input and the only way to connect it would be using an additional GPIO, like you mentioned in your original post. The CLB peripheral does have its own dedicated CLBINPUTXBAR and CLBOUTPUTXBAR, but they are simply used for routing the inputs and outputs, respectively, of the CLB directly to GPIOs. So to implement what you are trying to do, you would really have to find a way to reduce a GPIO

    Regards,

    Peter

  • 0 in reply to Peter Luong1
    Intellectual 390 points

    Thanks Peter, 

    But I actually found the path. You use the PWMXBAR MUX 1 to get the CLB 4 out. then set this up as a higher trip. Use the DC compare function to generate a sync pulse. Then, the final link in the chain was revealed to me by "Jason". Enable Phase Shift Load.

    So, this processor has LOTs of power. It requires LOTS of reading to learn what can be done. Study up!

    David

  • 0 in reply to david goodin
    TI__Genius 14171 points

    Awesome, glad you were able to get this clarified from Jason

    Regards,

    Peter