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TMS320F280039C: Jitter introduced by SYNC when using TBPRDHR

Wayne Huang
Genius 17145 points

Part Number: TMS320F280039C
Other Parts Discussed in Thread: TIDM-02002

Dear Champs,

I am asking this for our customer.

In TRM 20.15.1.5.4.1 High-Resolution Period Configuration, there is a note,

"When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2 cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count mode). For this reason, EPWMxSYNCO source should not be set to CTR = 0 or CTR = CMPB. Otherwise, the jitter will occur on every PWM cycle with the synchronization pulse. When EPWMxSYNCI is EPWMxSYNCO source, a software synchronization pulse should be issued only once during high-resolution period initialization. If a software sync pulse is applied while the PWM is running, the jitter will appear on the PWM output at the time of the sync pulse."

Questions:

1. It says "For this reason, EPWMxSYNCO source should not be set to CTR = 0 or CTR = CMPB." Does that mean the user can set other sources other than CTR=0 or CTR=CMPB?

For example, The user can still set 

EPWMSYNCOUTEN.CMPCEN = 1. Then set CMPC=0 to generate a EPWMxSYNCO. Can this setting avoid this issue?

2. For 2-phase interleaved EPWM, if the user uses EPWM1 to sync EPWM2.

EPWM1.EPWMSYNCINSEL.SEL=0 (Disabled)

EPWM1.EPWMSYNCOUTEN.ZEROEN = 1

EPWM1.TBCTL.PHSEN = 1

EPWM1.HRPCTL.TBPSHRLOADE = 1

EPWM2.EPWMSYNCINSEL.SEL = 1 (from EPWM1)

EPWM2.TBCTL.PHSEN = 1

EPWM2.HRPCTL.TBPSHRLOADE = 1

Then, does only EPWM2 suffer this jitter issue (sync from EPWM1) or "both EPWM1/EPWM2" suffer this jitter issue?

3. I am aware TIDM-02002 tried to have a workaround by enable/disable sync repetitively during runtime in ISR on F28004x. Because F28003x has introduced a new register TBCTL3.OSSFRCEN.

Can the user uses below concept to avoid this jitter issue?

TBCTL3.OSSFRCEN = 1 (reload by one-shot global load)

One-shot global load set to load shadow to active at CTR=0 to generate a EPWMxSYNCO at CTR=0 ONLY when period command (TBPRD/TBPRDHR) is updated.

TBPRD/TBPRDHR do not follow one-shot global load per the TRM request.

It should be similar to what has been shown in TIDM-02002, but with TBCTL3.OSSFRCEN.

Do you think it works to avoid this jitter issue?

  • 0
    TI__Mastermind 28580 points

    Hi Wayne,

    1. I doubt using CMPC would resolve this issue since the same note indicates that any EPWMSYNCOUT signal should only be used as a EPWMSYNCIN signal during high-resolution period initialization. I don't believe there are any functional differences in how events are generated between CMPC and CMPB.

    2. The jitter most likely occurs only on EPWM2 but I will confirm this with our other EPWM experts.

    3. From looking at Figure 20-7 in the F28003x TRM, the workaround you are describing here should have the same effect as the workaround in TIDM-02002. The only difference is rather than disabling synchronization on the EPWM module that is receiving the sync signal, the EPWM module that sends the sync source is sending a one-shot sync source.

  • 0 in reply to Luke Jones
    TI__Genius 17145 points

    Dear Luke,

    1. OK, I see. Looks like we have to confront with this note and cannot circumvent it.

    2. Please help check. That is, if only EPWM2 happens, then this workaround is not needed for a single EPWM HR period usage. For HR period, it's required to use below per 20.15.1.5.4.1 High-Resolution Period Configuration even though there is no SYNCIN for EPWM1.

    EPWM1.TBCTL.PHSEN = 1

    EPWM1.HRPCTL.TBPSHRLOADE = 1

    This is why we are confused.

    3. Yes, this is what I meant. Thanks for your confirmation.

  • +1 in reply to Wayne Huang
    TI__Mastermind 28580 points

    Hey Wayne,

    I looped Marlyn on this thread and she also believes only EPWM2 will be affected.

    I believe this is the key part of the note the customer should pay attention to: 

    "If a software sync pulse is applied while the PWM is running, the jitter will appear on the PWM output at the time of the sync pulse."

    So as long as the sync pulse is applied when the PWM is not running(the EPWM clock is disabled) there will be no jitter. Since the syncin source for EPWM1 is disabled(EPWM1.EPWMSYNCINSEL.SEL=0), EPWM1 will not be affected in this case.