TMS320F28379D: using TBPRDHR -> Jitter

I want to generate a PWM with high resolution duty and periode while using up count mode. I wrote a short program for a test, code below.

In up count mode (ZRO = out high; CAU = out low), I can use CMPAHR and it works fine for duty cycle. But if I wrote something in the TBPRDHR register, I get a jitter of one cycle instead of the high resolution peroid.

In up down count mode (CAU = out high, CAD = out low) I can use CMPAHR or (!) TBPRDHR for changing the duty cycle and period, all fine. But if I use any other AQ for changing the output, then I get also a jitter. For example I configure the AQ like (ZRO = high, CAU = low), like (CAU = high, CBD = low) or so on. Only when using ONLY CMPA for changing the output to high/low, then I can use TBPRDHR without getting the jitter.

Now my question: is it even possible to use TBPRD with another configuration as written above and if it is so, what's my mistake?

Thanks for help!

My code:

#include "F28x_Project.h"
#include "SFO_V8.h"

int MEP_ScaleFactor;
volatile struct EPWM_REGS *ePWM[PWM_CH] = {&EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs};

Uint16 PRD = 9, PRDHR = 0, CMPA = 5, CMPAHR = 0, CMPB = 5, CMPBHR = 0;

void pwm_cnfg(void);

void main(void)
{
	DINT;
	InitSysCtrl();
	InitPieCtrl();
	IER = 0x0000;
	IFR = 0x0000;
	InitPieVectTable();
	EINT;
	ERTM;

	while(SFO() == 0);

	InitEPwmGpio();
	pwm_cnfg();

	while(1)
	{
		EPwm1Regs.TBPRD = PRD;
		EPwm1Regs.TBPRDHR = PRDHR << 8;
		EPwm1Regs.CMPA.bit.CMPA = CMPA;
		EPwm1Regs.CMPA.bit.CMPAHR = (CMPAHR << 8);
		EPwm1Regs.CMPB.bit.CMPB = CMPB;
		EPwm1Regs.CMPB.bit.CMPBHR = (CMPBHR << 8);

		SFO();
	}
}

void pwm_cnfg(void)
{
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm1Regs.TBPRD = PRD;
	EPwm1Regs.TBPRDHR = PRDHR << 8;
	EPwm1Regs.CMPA.bit.CMPA = CMPA;
	EPwm1Regs.CMPA.bit.CMPAHR = (CMPAHR << 8);
	EPwm1Regs.CMPB.bit.CMPB = CMPB;
	EPwm1Regs.CMPB.bit.CMPBHR = (CMPBHR << 8);
	EPwm1Regs.TBPHS.all = 0;
	EPwm1Regs.TBCTR = 0;

	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
	EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
	EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
	EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x11;

	EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
	EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

	EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
	EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
	EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR;

	EPwm1Regs.HRCNFG.all = 0x0;
	EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;		// tried also HR_FEP and HR_REP
	EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
	EPwm1Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;
	EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP;
	EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
	EPwm1Regs.HRCNFG.bit.HRLOADB  = HR_CTR_ZERO_PRD;
	EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;
	EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
	EPwm1Regs.HRPCTL.bit.HRPE = 1;

	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
	EDIS;
}