Part Number: TIDM-02011
Other Parts Discussed in Thread: SYSBIOS, SFRA
I am using LDFU on DSP28F0049C. I set the same to DSP28F0039C, but address error occurs.
Please check if the setting method of DSP28F0049C and DSP28F0039C is different.
I would like to request an analysis of the cause of the live update setting error.
Please refer to the settings below.
ldfu setting err
- Error occurs when PMBusStack is added to apply TI PMBus library
- "address overrides" occurs when interanl support options are set to connect live update properties
□ error content
>> Compilation failure
makefile:216: recipe for target 'PCMC_PSFB_F28003x_KAIST330_bl89_4.out' failed
../../master/ELFLNK/collect.c:778:internal fatal error #10478: (.TI.bound:PMBusStack_commandTransactionMap)
INTERNAL ERROR: C:\ti\ccs1210\ccs\tools\compiler\ti-cgt-c2000_22.6.0.LTS\bin\lnk2000.exe had an internal inconsistency and aborted

Properties setting


--------------------------------------------------------------------------------------------------------
//
// Keep the _bankSelect symbol
//
-u bankSelect
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN_KERNEL : origin = 0x080000, length = 0x000200
BEGIN : origin = 0x08EFF0, length = 0x000004
C_INT_LFU : origin = 0x08EFF8, length = 0x000100
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
RAMM0 : origin = 0x00000128, length = 0x000002D8
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
RAMLS0 : origin = 0x00008000, length = 0x00000800
RAMLS1 : origin = 0x00008800, length = 0x00000800
RAMLS2 : origin = 0x00009000, length = 0x00000800
RAMLS3 : origin = 0x00009800, length = 0x00000800
RAMLS4 : origin = 0x0000A000, length = 0x00000800
RAMLS5 : origin = 0x0000A800, length = 0x00000800
RAMLS6 : origin = 0x0000B000, length = 0x00000800
RAMLS7 : origin = 0x0000B800, length = 0x00000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
//RAMGS0GS1 : origin = 0x00C000, length = 0x002000
RAMGS2 : origin = 0x0000E000, length = 0x00001000
RAMGS3 : origin = 0x0000F000, length = 0x00001000
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
RESET : origin = 0x003FFFC0, length = 0x00000002
/* Flash sectors */
//
// Allocate space for the liveDFU function in bank 0
//
//BANK0_SEC1 : origin = 0x081000, length = 0x000017
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080200, length = 0x000E00
FLASH_BANK0_SEC1 : origin = 0x081017, length = 0x000FE9
FLASH_BANK0_SEC234567 : origin = 0x082000, length = 0x006000 /* on-chip Flash */
FLASH_BANK0_SEC8910 : origin = 0x088000, length = 0x03000 /* on-chip Flash */
//FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
//FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
//FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
//FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
//FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
//FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
//FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
//FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
//FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x000FF0
FLASH_BANK0_SEC15 : origin = 0x08F0F8, length = 0x000F08
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
FLASH_BANK1_SEC234567 : origin = 0x092000, length = 0x006000 /* on-chip Flash */
FLASH_BANK1_SEC8910 : origin = 0x098000, length = 0x03000 /* on-chip Flash */
//FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
//FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
//FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
//FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
//FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
//FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
//FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
//FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
//FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
/* BANK 2 */
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
c_int_lfu_bank0 : > C_INT_LFU, ALIGN(8)
codestart_kernel : > BEGIN_KERNEL, ALIGN(8)
.text : > FLASH_BANK0_SEC234567 , ALIGN(8)
.cinit : > FLASH_BANK0_SEC8910, ALIGN(8)
.switch : > FLASH_BANK0_SEC8910, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMLS5
//#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC8910, ALIGN(8)
.bss : > RAMGS3, TYPE = NOINIT
//.bss:output : > RAMLS3
//.bss:cio : > RAMGS1
.data : > RAMGS2
.sysmem : > RAMLS4
.const : > FLASH_BANK0_SEC8910, ALIGN(8)
//#else
//.pinit : > FLASH_BANK0_SEC8910, ALIGN(8)
//.ebss : > RAMLS5
//.esysmem : > RAMLS5
//.cio : > RAMLS0
//.econst : > FLASH_BANK0_SEC8910, ALIGN(8)
//#endif
.TI.noinit: > RAMLS2
ramgs0 : > RAMLS6
ramgs1 : > RAMLS6
//.TI.ramfunc :
GROUP
{
.TI.ramfunc
{
//-l sfra_f32_tmu_eabi.lib
-l FAPI_F28003x_EABI_v1.58.00.lib
}
ramfuncs
dclfuncs
}
LOAD = FLASH_BANK0_SEC8910,
RUN = RAMGS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
//LDFU_BANK0 : > BANK0_SEC1, ALIGN(8)
FPUmathTables : > FLASH_BANK0_SEC0
}
-------------------------------------------------------------------------------------------------------
MEMORY
{
BEGIN : origin = 0x09EFF0, length = 0x00000004
C_INT_LFU : origin = 0x09EFF8, length = 0x000100
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
RAMM0 : origin = 0x00000128, length = 0x000002D8
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
RAMLS0 : origin = 0x00008000, length = 0x00000800
RAMLS1 : origin = 0x00008800, length = 0x00000800
RAMLS2 : origin = 0x00009000, length = 0x00000800
RAMLS3 : origin = 0x00009800, length = 0x00000800
RAMLS4 : origin = 0x0000A000, length = 0x00000800
RAMLS5 : origin = 0x0000A800, length = 0x00000800
RAMLS6 : origin = 0x0000B000, length = 0x00000800
RAMLS7 : origin = 0x0000B800, length = 0x00000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
//RAMGS0GS1 : origin = 0x00C000, length = 0x002000
RAMGS2 : origin = 0x0000E000, length = 0x00001000
RAMGS3 : origin = 0x0000F000, length = 0x00001000
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
RESET : origin = 0x003FFFC0, length = 0x00000002
/* Flash sectors */
//
// Allocate space for the liveDFU function in bank 1
//
//BANK1_SEC1 : origin = 0x91000, length = 0x000017
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080200, length = 0x000E00
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
FLASH_BANK0_SEC234567 : origin = 0x082000, length = 0x006000 /* on-chip Flash */
FLASH_BANK0_SEC8910 : origin = 0x088000, length = 0x03000
//FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
//FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
//FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
//FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
//FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
//FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
//FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
//FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
//FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090002, length = 0x000FFE
FLASH_BANK1_SEC1 : origin = 0x091017, length = 0x000F39
FLASH_BANK1_SEC234567 : origin = 0x092000, length = 0x006000 /* on-chip Flash */
FLASH_BANK1_SEC8910 : origin = 0x098000, length = 0x03000 /* on-chip Flash */
//FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
//FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
//FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
//FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
//FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
//FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
//FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
//FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
//FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x000FF0
FLASH_BANK1_SEC15 : origin = 0x09F0F8, length = 0x000F08
/* BANK 2 */
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
c_int_lfu_bank1 : > C_INT_LFU, ALIGN(8)
.text : > FLASH_BANK1_SEC234567 , ALIGN(8)
.cinit : > FLASH_BANK1_SEC8910, ALIGN(8)
.switch : > FLASH_BANK1_SEC8910, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMLS5
//#if defined(__TI_EABI__)
.init_array : > FLASH_BANK1_SEC8910, ALIGN(8)
.bss : > RAMGS3, TYPE = NOINIT
//.bss:output : > RAMLS3
//.bss:cio : > RAMGS1
.data : > RAMGS2
.sysmem : > RAMLS4
.const : > FLASH_BANK0_SEC8910, ALIGN(8)
//#else
//.pinit : > FLASH_BANK1_SEC8910, ALIGN(8)
//.ebss : > RAMLS5
//.esysmem : > RAMLS5
//.cio : > RAMLS0
//.econst : > FLASH_BANK1_SEC8910, ALIGN(8)
//#endif
.TI.noinit: > RAMLS2
.TI.update: > RAMGS3
ramgs0 : > RAMLS6
ramgs1 : > RAMLS6
//.TI.ramfunc :
GROUP
{
.TI.ramfunc
{
//-l sfra_f32_tmu_eabi.lib
-l FAPI_F28003x_EABI_v1.58.00.lib
}
ramfuncs
//dclfuncs
}
LOAD = FLASH_BANK1_SEC8910,
RUN = RAMGS1,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
//LDFU_BANK1 : > BANK1_SEC1, ALIGN(8)
FPUmathTables : > FLASH_BANK1_SEC0
}













