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Original question:

TMS320F28335: TMS320F28335: PID Simulation (DCL)

TMS320F28335: PID (DCL)

Muhammad Arsalan Athar
Intellectual 410 points
Part Number: TMS320F28335

Hi I am continuing with my last post because I can not see the reply option there. I was absent for some reason for some days, couldn't reply the last thread and it was locked now. So here I am attaching the last thread to continue. 

TMS320F28335: TMS320F28335: PID Simulation (DCL) - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

My concern was that yk is well outside of the range of +/-1, it was showing 12.9f on IMAGE 5 and it shouldn't be the case. If we do a quick calculation, P-path's control effort would be abs(yk - rk) * Kp = (12.9 - 0.25) * 9  =  113.85, which would be clamped to 1.

Question 1:

Here I see yk at 0V is 0 but yk at 1.2V is 12.9. it must clamped to +/-1 for ADC value 0 at 0V and 4095 at 3V over extreme values as shown in pictures. The previous replies explain that the controller at kp =9 is overreacting and showing the maximum control effort . I want to confirm that, should I set the Kp or other control parameters to make the yk = +/-1 ? If  you check in DCL guide example 3,4 &5. rk can be change, uk could be change yk must be in between -1 & +1. What changes should I do to keep it  between +1 and -1 ?

Currently, do you have any feedback mechanism that allows you to use the duty cycle and influence your adc input? If there isn't any feedback, PID controller will never be able to reach the target voltage and its I-path would eventually saturate the feedback. And if you don't have a consistent input influence, the controller would eventually settle at 0% as it reaches the target value. The only way for a controller to constantly provide a control effort is if you have an constantly applied influence to begin with.

Question 2:

I am implementing this circuit which is shown in the picture below. Input Vin is 20V DC and output Vout is 10V constant DC in the Buck converter physical plant model. But here I am separating the above plant model for my test from the feedback part and then providing a 0-3V DC output from the external power supply. The feedback part will generate an ePWM signal having duty cycles for the gate transistor (Gate Driver). As I said before that I am removing the above Buck plant model and then will check this changing duty cycle signals through oscilloscope based of my 0-3V DC supply. Here I can change my supply values for output like 0V, 1V, 1.5V, 2V etc  and will see the effect duty cycles accordingly.  Is it necessary now to connect plant model with Feedback part for my initial setup having PID mechanism? will the PID be able to reach the target value(Vref value) at this setup having no Plant model but only using external power supply 0-3V and then check  the simulation on hardware ?

If you just need proportional duty cycles based on ADC readings, you don't need a PID to achieve that, directly assigning ADC reading to the duty cycle register would suffice, provided no external influence to the system.

Question 3:

For this condition, I need to make formula/relation between ADC vs duty cycle where ADC has two extreme values 0 (0V) and 4095(3V) and  the duty cycle 0 and 100% respectively.  If any such value achieves like 1.2V or 1638 digital value then duty cycle would roughly be around 45% or 40% in between. This formula could be implemented in my code but  the problem is that there will be no clamping/saturation or anti windup reset setup in case of your output goes high at the startup of Buck Converter Plant model and you need to settle at one value. This was the reason that I am using PID which can control the output and settle at one value with respect to reference/set value Vref. 

uk/2.0f + 0.5f was an attempt to normalize the control output range from -1.0~1.0f to 0~1.0f, representing 0% to 100% of the duty cycle.

Question 4:

What does ~ means? Does it means -1 to +1? and how it equals to 0 ~ 1? As i know this formula yk = ((float) AdcRegs.ADCRESULT0 - 2048.0f) / 2047.0f; it gives yk values between -1 to +1? so how it can equal to 0 ~ 1? 

Question 5

I am attaching a code here. With this program, there will be no middle value in duty cycle I can get as you said before either you will have 0% duty or 100% duty cycle using PID controller. One thing i noticed in DCL guide example 3,4,& 5. lk is always 1.0 not 0. But in my case it remains 0 all the time. why?

At 0V, Duty is 65535.0

At 3V, Duty is 0

At 1.2V, Duty is 0.


Please suggest the answers for above questions accordingly.

Thanks

Regards

Arsalan

  • +1
    TI__Intellectual 2236 points

    Hi Arsalan,

    Welcome back to the forum, good to see you here! Let me answer your questions in the same order:

    1. Normally when you don't scale down your input (feedback response yk), Kp should be scaled down to compensate the control effort abs(yk-rk)*Kp. But in your case, line 309 should have taking care of yk by scaling it to +/-1, can you double check by tracing through the code and see if yk is indeed scaled to +/-1 right after line 309?

    2. Sorry I couldn't see the attached image for some reason, but thank you for the clarification. You can test out the PID model without the Buck plant model. Nonetheless you have to be very meticulous with your testing as you have to simulate your ADC value based on the controller output. I would suggest using breakpoints in the ISR routine, so that you can observe the uk output while provide an appropriate ADC input for the next ISR cycle. If you provide an constant ADC value through out each cycle, the controller will (either P-path saturates right away or I-path eventually saturates) output an saturated control effort uk and that is why you see the maximum/minimum uk values regardless of your tuning. 

    3. Got it, what I would suggest in your case is to provide an additional offset base on your ADC value. It would be your base Duty Cycle value so your output isn't 0% when the controller is in steady-state. For instance, when your ADC is say 2048 and the controller is in steady-state (output uk is 0%), then you could add an offset of 50% to make sure duty cycle is 50%. Your offset value will be what you wanted the duty cycle to settle in, and for your scenario a simple interpolation value works just fine (offest  = yk/2.0f + 0.5f after line 309). Do keep in mind that uk+offset needs to be clamped to prevent it exceed out of range.

    4. Yes, apologies for the misuse of symbols here. Both internal and external clamp made sure uk stays within +/-1.0f, when uk is 1, uk/2.0f+0.5f converts it to 1, when uk is -1, it converts it to 0. 

    5. lk = 0 is an indication of your control output being saturated, refer to line 317. lk is a measurement of anti-windup, when lk is 0, the I-path value would be disregarded in the controller computation.

    Best,

    Sen Wang

  • 0 in reply to Sen Wang
    Intellectual 410 points

    Dear Seng,

    Thanks for your comprehensive replies for all questions. Here I refer only Question 1 and Question2 only.

    1. Normally when you don't scale down your input (feedback response yk), Kp should be scaled down to compensate the control effort abs(yk-rk)*Kp. But in your case, line 309 should have taking care of yk by scaling it to +/-1, can you double check by tracing through the code and see if yk is indeed scaled to +/-1 right after line 309?

    2. Sorry I couldn't see the attached image for some reason, but thank you for the clarification. You can test out the PID model without the Buck plant model. Nonetheless you have to be very meticulous with your testing as you have to simulate your ADC value based on the controller output. I would suggest using breakpoints in the ISR routine, so that you can observe the uk output while provide an appropriate ADC input for the next ISR cycle. If you provide an constant ADC value through out each cycle, the controller will (either P-path saturates right away or I-path eventually saturates) output an saturated control effort uk and that is why you see the maximum/minimum uk values regardless of your tuning. 

    Now I am adding results and some questions here based on your answers. As you recommended, in order to check the operation, I use the breakpoints at yk,lk,uk,duty. and press debug(green button) each time and see the results. The array Voltage1 is updating bitwise (0-9)

    At 0 Voltage (0) input (ADCAN0): From Pictures adc1.jpg to adc5.jpg. What I noticed is that array Voltage1(0-9) bits is updating its values bitwise, the uk stays at  +/-1. which is correct, yk is at 0,745 approx to 0. lk = 1 and duty is either 65535 or 0, and uk also changes according +/-1.  All values of Voltage1 array are changed bitwise sequentially (step by step) starts from 0 then 1,2,..9 until.

    At 3V Voltage(4095) input (ADCAN0): From Pictures adc6.jpg to adc10.jpg. What I noticed is that array Voltage1(0-9) bits is updating its values bitwise, the uk stays at  +/-1. which is correct, lk = 1 and duty is either 65535 or 0, and uk also changes according +/-1. All values of Voltage1 array are changed bitwise sequentially (step by step) starts from 0 then 1,2,..9 until. 

    The Problem is at 3V Voltage(4095) input (ADCAN0) , the yk always remains at 31. How can I fix this?

     adc1.jpg

    adc2.jpg

    adc3.jpg

    adc4.jpg

    adc5.jpg

    adc6.jpg

    adc7.jpg

    adc8.jpg

    adc9.jpg

    adc10.jpg

    Please suggest the answers accordingly

    Thanks

    Kind Regards

    Arsalan

  • +1 in reply to Muhammad Arsalan Athar
    TI__Intellectual 2236 points

    Hi Arsalan,

    This question pertains to interior code logic so I can't dive in without replicating your code. But the yk calculation seems way off, if you were to hand calculate the yk value based on the reading, you'll see that it should have been way smaller than 0.75, same goes for when yk is 31.

    The only suggestions I have is to double check your AdcRegs.ADCRESULT0 reading, and double check to make sure yk isn't changed by other instance. The issue regards to your programming logic and it would be up to your judgement to resolve the issue.

    Best,

    Sen Wang

  • 0 in reply to Sen Wang
    Intellectual 410 points

    Hi Seng,

    Thanks for your replies and suggestions. It seems working now as expected. Many Thanks!.

    You were right about the checks on AdcRegs.ADCRESULT0. The problem was the AdcRegs.ADCRESULT0 value which was 65320 at 3V input(see picture). and yk = ((float) AdcRegs.ADCRESULT0 - 2048.0f) / 2047.0f never gives you -/+1.

    So I just divided this value : (float) AdcRegs.ADCRESULT0 by 16 to keep the y in a range of +/-1.

    I have one more question related to reference change. Please check the post below. 

    The results are collected below using breakpoints: 

    1- At 0V (Using Breakpoints) :

    Picture adc11.jpg and adc12.jpg give uk changes as -/+1 , duty change is like either 1250 (I have changed my TBPRD for 120Khz = 1250) 0r 0. (duty 0 or 1250) and most important yk =-0.9 approx -1,

    adc11.jpg

    adc12.jpg

    2- 1- At 3V (Using Breakpoints):

    Picture adc13.jpg and adc14.jpg give uk changes -/+1 , duty change is like either 1250 (I have changed my TBPRD for 120Khz = 1250) 0r 0. (duty 0 or 1250) and most important yk = +1,

    adc13.jpg

    adc14.jpg

    Now I am having few questions;

    Above pictures use reference values at 0.25. When I change the rk values from 0.25 to 2.0 or any other value more than 0.25 then It doesn't make any changes in results. What could be the change I can realize if I select different reference values? Please explain this:

    Below all 4 pictures...adc21.jpg, adc22.jpg, adc23.jpg, adc24.jpg are the ones using reference values 2.0. 

    At 0V (Using Breakpoints): adc21.jpg

    At 0V (Using Breakpoints): adc22.jpg

    At 3V (Using Breakpoints): adc23.jpg

    At 3V (Using Breakpoints): adc24.jpg

    Please suggest the answers accordingly

    Thanks 

    Kind Regards

    Arsalan

  • +1 in reply to Muhammad Arsalan Athar
    TI__Intellectual 2236 points

    Hi Arsalan, 

    Glad that you solved the problem! I also neglected line 306&307 for ADC readings, which is suggesting the value should be divided by 2^4.

    Back to your concern, please refer back to the original response to your question 2 on this thread. The reason you're not seeing any uk changes is explained there. Therefore you must feed in appropriate ADC values as described to see non-saturated uk values.

    Furthermore, a simple P-path calculation can be described as abs(yk-rk)*kp and it is clamped by upper/lowerLim . Since your Kp value is 9.0f and your upper/lowerLim is +/-1.0f. Your abs(yk-rk) would be 1/9. Meaning a yk,rk difference of greater than 0.111 will saturate your control effort. As such, you probably need to tinker around with PID parameters in order to obtain your optimal results.

    Best,

    Sen Wang

  • 0 in reply to Sen Wang
    Intellectual 410 points

    Hi Sen,

    Thanks for your reply. I will post another thread for tuning the pid and will discuss about the response plots for uk,yk,e,and lk once I collect more data.

    Thanks

    Kind Regards

    Arsalan