• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 81 subscribers
  • Views 148 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280039: CLB module delay problem

Ben Qin
Intellectual 2685 points
Part Number: TMS320F280039

Hi Team,

There's an issue from the customer need your help:

We use the CLB module in the application, the purpose is to configure EPWM8B to a specific IO pin through CLB, the IO pin itself cannot be configured as an epwm port. The configuration is as follows: The output of the EPWM8B AQ module is used as the input of CLB_IN4, and the output of CLB output6 is configured to the IO pin through the CLBoutputxbar. It is found that the driving waveform after the CLB module has a fixed delay (23ns) compared to the original epwm8B module. Is there any way to solve it? Thanks!

Best Regards,

Ben

  • 0
    TI__Mastermind 30180 points

    Hello Ben,

    It looks like you have the input synchronization enabled, this itself adds 2-3 clock cycles delay to whatever input is coming in (which is approximately the delay you're seeing). Keep in mind that this is normally required if you're doing any synchronized logic (i.e. comparing timer values, etc.) with an unsynchronized signal like the ePWM. If you are just simply routing the signal through the CLB to be able to route it to a certain GPIO pin, you can disable this.

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    TI__Intellectual 2685 points

    Hi Omer,

    Thanks Reply! According to your reply, I disabled the CLB synchronization, and the delay will indeed be reduced, but there will still be a 10ns delay. Is this the inherent delay of the CLB module? Is there any way to remove it?

    Below is my changed configuration:

    Best Regards,

    Ben

  • 0 in reply to Ben Qin
    TI__Mastermind 30180 points

    Hello Ben,

    If you have no synchronization or pipeline filter and are still seeing a delay, I will need to check with the design team on what this may be from. As another question, how are you measuring this delay? Do you have an ePWM with the same configuration as the one configured with the CLB and are just comparing the outputs against each other?

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    TI__Mastermind 30180 points

    Hello Ben,

    I have confirmed that actually the outputs of the CLB are almost all registered as well. So depending on which output you are using for the CLB, there will be a delay. For the F28003x device, CLBx_OUT12 through CLBx_OUT15 should be unregistered and asynchronous to the CLB clock. This is documented in the technical reference manual:

    Best regards,

    Omer Amir