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Hello,
I saw from another post that the I2C peripheral in the C2000 processors works in repeat mode even in master-receive mode, despite the indication of the RM bit from the I2CMDR register in the TRM.
In order to ensure that it works, we prototyped it on one of our board.
We did the following:
The slave device then continuously transmit bytes which are then stored into the FIFO and we unpack them fast enough to avoid the FIFO from getting full.
As this behavior is not documented, can you please confirm that this behavior is as expected and will always work, as well as maybe request a documentation update ?
Best regards,
Clément
Hello Clément,
I've contacted the designers to confirm this behavior and see if there is a reason we don't mention the master-receive configuration for repeat mode. I will reply some time mid-next week if I have a response.
Best regards,
Omer Amir
Apologies for the extended delay, I'm still in discussion to confirm with the design team, it seems like the I2C is expectedly capable of this, but for some reason we haven't documented this. I'm still confirming the reason for this.
I have confirmed with the design experts that the I2C is capable of this, and in fact this seems to be documented in most places in the TRM except the RM register bit description. I will file a change for this, and the device TRM should reflect this in its next update.