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Original question:
TMS320F280049: I2C Repeated Start Behavior / RM bit / Accurate RX Count
Hello,
I saw from another post that the I2C peripheral in the C2000 processors works in repeat mode even in master-receive mode, despite the indication of the RM bit from the I2CMDR register in the TRM.
In order to ensure that it works, we prototyped it on one of our board.
We did the following:
The slave device then continuously transmit bytes which are then stored into the FIFO and we unpack them fast enough to avoid the FIFO from getting full.
As this behavior is not documented, can you please confirm that this behavior is as expected and will always work, as well as maybe request a documentation update ?
Best regards,
Clément
