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TMS320F28033: What circumstances would cause this PWM count//TBCTR to be out of sync in all PWM module?

Shaoxing Ke
Expert 3590 points
Part Number: TMS320F28033

Hi Experts,

I am asking for my customer.

Phenomenon: Customer/They use F28033 to do PSU, and they do PWM init missed the TBCTR  = 0x0000 in the all PWM module. When they tested the code under half load condition, PWM1 and PWM2 The PWM1 and PWM2 modules are out of sync by 5 TBCLKs. 

You can refer the below PWM init code, they do not initialize the TBCTR, but they have followed the Time-Base Clock Synchronization below, and also S/W force Software synchronization. Therefore, in theory, all PWM modules should start working at the same time, and Time-Base (TB) Submodule are also synchronous.

1).We test the code on our EVM or customer's board without load condition, PWM1 and PWM2 PWM1 and PWM2 are synchronized, but we test the code under half load condition, PWM1 and PWM2 The PWM1 and PWM2 modules are out of sync by 5 TBCLKs, not synchronized. 

2).If we add to initialize the TBCTR  = 0x0000 in the all PWM module, All PWM modules are synchronized in any case (Load condition). Meanwhile, everything looks work well. So, If TBCTR is not clear when PWM is initialized, are there any risks? What circumstances would cause this PWM count//TBCTR to be out of sync in all PWM module? Thanks.

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void InitEPwm1(void)
{
// EPWM1 config
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // up/down Count
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//TBPRD is loaded from its shadow register on Counter = 0 event (CTR_zero)
//TBCLK=SYSCLKOUT/(HSPCLKDIV * CLKDIV)=SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; //Timebase clock pre-scale
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High speed time pre-scale
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 0; // enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm1Regs.ETCLR.all = 0x000F ; //clear all ETFLAG
EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Mastermind 21180 points

    Hi Shaoxing,

    It is always best practice to initialize the EPWM time base counter to a value (i.e. TBCTR = 0x000) when setting up the module in initialization. This is the best way to ensure the modules are started properly. Also note that there will always be some inherent delay in synchronization as described in the TRM section 3.2.2.3.3 Time-Base Counter Synchronization under "EPWMxSYNCI: Synchronization Input Pulse", which can be accommodated for by using TBPHS to adjust for this and generate perfectly synced PWMs (similarly seen on other devices as referenced in this thread). I think here it might be that by setting TBCTR=0 for the EPWM may allow for EPWM2 synchronization to occur when this is carried out (since EPWM2 is using EPWM1 SYNCOUT). What is the EPWM1 sync-in source? As for the cause of the delay you are seeing with the half load vs without, I don't see why the PSU system load would affect this, but setting TBCTR=0 should be done regardless.

    Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 3590 points

    Hi Allison,

    Right. We are also curious about this issue case. We do not know why the PWM1 and PWM2 modules are out of sync by 5 TBCLKs under load condition.

    Actually, we test the code on customer's board without condition, the PWM1 and PWM2 are always Sync. So, hard to know why has this difference? 

    And even if the Synchronization Input Pulse delay only 2 TBCLK, but we scope it has 5 TBCLKs delay. Why this? Thanks.

  • 0 in reply to Shaoxing Ke
    TI__Expert 3590 points

    Hi Allison,

    You can see the below code about EPWM2 init, customer also has setup the TBPHS.

    EPwm2Regs.TBPHS.half.TBPHS = 1;  I would let customer try the TBPHS  = 2 to verify the issue.

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    void InitEPwm2(void)
    {
    // EPWM2 config
    EPwm2Regs.TBPRD = EPWM1_TIMER_TBPRD;
    EPwm2Regs.TBPHS.half.TBPHS = 1;
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_ENABLE;//lzy for TBPRDHR
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
    EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; //Phase Direction Down
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // up/down Count
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    //TBCLK=SYSCLKOUT/(HSPCLKDIV * CLKDIV)=SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //Timebase clock pre-scale
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High speed time pre-scale
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on Prd event
    EPwm2Regs.ETSEL.bit.INTEN = 0;// Disable INT
    EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
    EPwm2Regs.ETCLR.all = 0x000F ; //clear all ETFLAG
    EPwm2Regs.CMPA.half.CMPA = EPWM1_MAX_CMPA;//lzy 20091228
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Shaoxing Ke
    TI__Mastermind 21180 points

    Hi Shaoxing,

    Hard to tell the exact cause of why it would behave differently under load, but one theory is perhaps the 5 TBLCK delay could have something to do with the compensator during applied load and the frequency of control loop- or maybe there is some exacerbation of the existing inherent delay, but it is hard to be sure for that exact hardware setup. Regardless, it is still best to set TBCTR=0 for initialization, and the use of TBPHS with this as mentioned should omit the inherent delay. Let me know if the customer sees different results with different TBPHS values, and please let me know if you have further inquiries here.

    Best regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 3590 points

    Hi Allison,

    Actually, I do not know this case here. Could you give us more detailed info.

    Allison Nguyen said:
    but one theory is perhaps the 5 TBLCK delay could have something to do with the compensator during applied load and the frequency of control loop- or maybe there is some exacerbation of the existing inherent delay,

  • 0 in reply to Shaoxing Ke
    TI__Mastermind 21180 points

    Hi Shaoxing,

    That theory was just my very initial thoughts on this, but I am honestly not too familiar with why an electronic load would affect the TBCLK delay. Please let me consult with other PWM experts on this, and I will back to you with more information by end of day today or Monday at the latest.

    Best regards,

    Allison

  • 0 in reply to Shaoxing Ke
    TI__Mastermind 21180 points

    Hi Shaoxing,

    I have a few more questions first to get a better idea here: Are you able to share some more of the software flow/ISR code to know what else is being done in the program? Is there any anything in the software that is dependent on the load (i.e. are there any actions being taken in software under certain load conditions)?

    Best Regards,

    Allison