Hi Experts,
I am asking for my customer.
Phenomenon: Customer/They use F28033 to do PSU, and they do PWM init missed the TBCTR = 0x0000 in the all PWM module. When they tested the code under half load condition, PWM1 and PWM2 The PWM1 and PWM2 modules are out of sync by 5 TBCLKs.
You can refer the below PWM init code, they do not initialize the TBCTR, but they have followed the Time-Base Clock Synchronization below, and also S/W force Software synchronization. Therefore, in theory, all PWM modules should start working at the same time, and Time-Base (TB) Submodule are also synchronous.
1).We test the code on our EVM or customer's board without load condition, PWM1 and PWM2 PWM1 and PWM2 are synchronized, but we test the code under half load condition, PWM1 and PWM2 The PWM1 and PWM2 modules are out of sync by 5 TBCLKs, not synchronized.
2).If we add to initialize the TBCTR = 0x0000 in the all PWM module, All PWM modules are synchronized in any case (Load condition). Meanwhile, everything looks work well. So, If TBCTR is not clear when PWM is initialized, are there any risks? What circumstances would cause this PWM count//TBCTR to be out of sync in all PWM module? Thanks.
void InitEPwm1(void)
{
// EPWM1 config
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // up/down Count
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//TBPRD is loaded from its shadow register on Counter = 0 event (CTR_zero)
//TBCLK=SYSCLKOUT/(HSPCLKDIV * CLKDIV)=SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; //Timebase clock pre-scale
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High speed time pre-scale
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 0; // enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm1Regs.ETCLR.all = 0x000F ; //clear all ETFLAG
EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; //for Piccolo HRPWM AQ_SET
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
//Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DBB_ENABLE; //S1=1,S0=0
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; //S3=0,S2=0
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; //S5=1,S4=0
EPwm1Regs.DBRED = DC_DB_TIME_300NS; //DC_DB_TIME_100NS;
EPwm1Regs.HRCNFG.all = 0x0;//lzy
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;//rising and falling edge
EPwm1Regs.HRCNFG.bit.AUTOCONV = AUTOCONV_AUTO; // Enable autoconversion
EPwm1Regs.HRPCTL.bit.HRPE=0x01; // Turn on high-resolution period control.
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
}
