F28035 TBCTR sync misses PWM Zero events!?

Hmmm, no answers yet. Can we provide any additional information that might help?

Hi Stephan,

Could you post your PWM initialization code here so that we can further understand your setup? Also, can you describe how you are updating the PWM period and/or post the code as well?

Thanks,

Kris

Okay, here is our setup:

EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm1Regs.TBCTL.bit.PHSDIR = 1; // Count up after sync event
EPwm1Regs.TBCTL.bit.SYNCOSEL = 3; // No sync out
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT: div by 1
EPwm1Regs.TBCTL.bit.CLKDIV = 0;

EPwm1Regs.TBPRD = 6000;
EPwm1Regs.TBPHS.all = 0;
EPwm1Regs.TBCTR = 0;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // Load registers every ZERO, shadowed
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;

// Setup compare
EPwm1Regs.CMPA.all = 5;
//EPwm1Regs.CMPB = 2;

// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = 2; // Set PWMA on zero event
//EPwm1Regs.AQCTLA.bit.CBU = 2; // Set PWMA on CompareB (upcount)
EPwm1Regs.AQCTLA.bit.CAU = 1; // Clear PWMA on CompareA (upcount)

EPwm1Regs.AQCTLB.bit.ZRO = 2;
EPwm1Regs.AQCTLB.bit.CAU = 1;

// Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = 3;
EPwm1Regs.DBCTL.bit.POLSEL = 2;
EPwm1Regs.DBCTL.bit.IN_MODE = 0;
EPwm1Regs.DBRED = 18;
EPwm1Regs.DBFED = 18;


// Trip Zone for PWM1 (comparator 3 as period sync event, TZ1/OSHT via Force as enable/disable PWM)
// Define an event
EALLOW;
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 10; // DCAH = Comparator 3 output
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; // DCAEVT1 = DCAH high (will become active as Comparator output goes high)
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // DCEVT source is DCEVT, unfiltered
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // Take async path for TZFRC
EPwm1Regs.DCACTL.bit.EVT1SYNCE = 1; // DCAEVT1 Sync Enable


EPwm1Regs.TripZoneControl.bit.TZA = 2; // EPWMA will be forced low on a trip event (for switching PWM OFF)
EPwm1Regs.TripZoneControl.bit.TZB = 2; // EPWMB will be forced low on a trip event (for switching PWM OFF)
EPwm1Regs.TripZoneControl.bit.DCAEVT1 = 3;
EPwm1Regs.TripZoneControl.bit.DCAEVT2 = 3;
EPwm1Regs.TripZoneControl.bit.DCBEVT1 = 3;
EPwm1Regs.TripZoneControl.bit.DCBEVT2 = 3;

// Setup Event Filtering / Blanking Window for DCAEVT
EPwm1Regs.DCFCTL.bit.BLANKE = 1; // Blanking Window enable
EPwm1Regs.DCFCTL.bit.PULSESEL = 1; // Start blanking window on timer equal zero
EPwm1Regs.DCFCTL.bit.SRCSEL = 0; // Source for blanking window is DCAEVT1 (OST)
EPwm1Regs.DCFOFFSET = 0; // start blanking window without offset/delay
EPwm1Regs.DCFWINDOW = 30; // blanking window width in TBCycles

EPwm1Regs.TZSEL.bit.OSHT1 = 1; // Enable TZ1 as OST trip event (will only be set via EPwm1Regs.TripZoneForce.bit.OST = 1, no TZ1 on pins)
EPwm1Regs.TZSEL.bit.OSHT2 = 1; // Overcurrent disables PWM // For switching PWM OFF

EPwm1Regs.TripZoneClear.AsWord = 0xFFFF;
EPwm1Regs.TripZoneForce.bit.OST = 1; // initially disable Switches

EDIS;
-----------------------------------

PWM1 period is not updated/changed, only phase synched via DCAEVT/Comparator3 current limit.
PWM1 compareA is updated every 50usec, asynchronous to PWM1.
We get missing pulses on PWM1A sometimes.
It seems as if the sync pulse sometimes suppresses the "force high on counter=zero" event.
After adding the 2 commented lines for compareB
EPwm1Regs.CMPB = 2;
EPwm1Regs.AQCTLA.bit.CBU = 2; // Set PWMA on CompareB (upcount)
the missing pulses are gone.

Best regards,
Stephan

Hi Stephan,

CMPB = 2 and PWMA configured to SET on CBU seems to be bringing back all the pulses, which suggests the syncing mechanism is working. As you said something seems to be overriding the SET on ZRO action. I have my suspicions on the TZCTL setting. Please make sure that the TZCTL[DCAEVT1] bit is configured to 'do nothing' (11b). In fact it is a good practice to configure all unused options in TZCTL registers to 'do nothing'.

BTW I noticed that you have configured blanking window but it looks like you are (possibly unintentionally) not using it. To use blanking window DCACTL[EVT1SRCSEL] should be set to 1.

I hope this helps.

Hrishi

Hi Hrishi,

blanking window is switched off intentionally because it did not work as we expected. I will look at this further and open another thread about this.

Regarding the missing pulses: We are changing actions asynchronsously when switching from pos to neg halfwave. Since the AQCTLx registers are not shadowed on the 28035, the PWM channels are switched off during this time. But we just saw that the switch off time may not be long enough.
I will check this again.

Stephan

Stephan,

Please let me know what you find. Setting unused options in TZCTL to 'do nothing' should help.

I will reply to your other post as well.

Hrishi