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TMS320F28034: Behavior when conflicting ePWM between TBCTR write and TBCTR sync event occurring

Hisao Uchikoshi
Genius 15480 points

Part Number: TMS320F28034

Hi Experts,

ePWM2 is configured as synchronization with ePWM1(EPWM2SYNCI) by setting TBCTL[PHSEN] to 1. When a software is attempting to write new TBCTR on ePWM2 at just receiving EPWM2SYNCI input, what happens?

case 1) ePWM2 TBCTR is synchronized to the value of TBPHS at the next edge of TBCLK and continue to increment the count. Thus, writing TBCTR is ignored.

case 2) ePWM2 TBCTR is updated to new written data  at the next edge of TBCLK and continue to increment the count. Thus, Sync event is ignored and TBPHS data is not uploaded to TBCTR.

Regards,

Uchikoshi