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Hi Experts,
ePWM2 is configured as synchronization with ePWM1(EPWM2SYNCI) by setting TBCTL[PHSEN] to 1. When a software is attempting to write new TBCTR on ePWM2 at just receiving EPWM2SYNCI input, what happens?
case 1) ePWM2 TBCTR is synchronized to the value of TBPHS at the next edge of TBCLK and continue to increment the count. Thus, writing TBCTR is ignored.
case 2) ePWM2 TBCTR is updated to new written data at the next edge of TBCLK and continue to increment the count. Thus, Sync event is ignored and TBPHS data is not uploaded to TBCTR.
Regards,
Uchikoshi
Uchikoshi-San,
I am looking into this, I will post again.
My first question... Why is your software writing directly to the TBCTR?
Regards,
Cody
Uchikoshi-San,
The CPU write has priority over a SYNCI event. This means the device would function as you described in Case2.
Regards,
Cody