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Hello I'm experiencing a duty cycle issue during the phase transition, and I would like to hear your opinions.
I'm using updown counter for all EPWM channel. The orange represents EPWM3, and the gray represents EPWM4 channels. I've set EPWM1 as a reference to adjust the phase of EPWM3 and EPWM4. In the section of the image, the duty cycle of EPWM3 is approximately d3=0.1, and EPWM4 should switch complementarily with 1-d3.
However, the issue arises in the highlighted red rectangle. The duty cycle of EPWM3 should be around 0.1, but suddenly it becomes 1 in that region. Despite limiting the duty cycle of EPWM to a maximum of 0.5, it unexpectedly reaches 1. This problem doesn't persist but occurs sporadically even though it generally operates well.
This problem seems to occur when using phase shift, and it works fine when phase shift is not applied. Moreover, during this time, when the phase transitions from positive to negative, it seems to have an impact.
please see the code below.
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//EPWM set
// Updown
ePWM_Regs[ch]->AQCTLA.bit.CAD = AQ_SET;
ePWM_Regs[ch]->AQCTLA.bit.CAU = AQ_CLEAR;
ePWM_Regs[ch]->AQCTLB.bit.CAD = AQ_SET;
ePWM_Regs[ch]->AQCTLB.bit.CAU = AQ_CLEAR;
if(ch==1 ){
ePWM_Regs[ch]->TBCTL.bit.PHSEN = 0;//TB_DISABLE;
ePWM_Regs[ch]->TBCTL.bit.SYNCOSEL =1;// TB_CTR_ZERO;
}
else if(ch!=1) {
ePWM_Regs[ch]->TBCTL.bit.PHSEN = 1;//TB_ENABLE;
ePWM_Regs[ch]->TBCTL.bit.SYNCOSEL = 0;//TB_SYNC_IN;
}
SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 0x2; //(enable)
// Setup TBCLK
ePWM_Regs[ch]->TBCTL.bit.CTRMODE = 2;//TB_COUNT_UPDOWN; // Count up-down
ePWM_Regs[ch]->TBCTL.bit.PRDLD = 0;//TB_SHADOW;
ePWM_Regs[ch]->TBCTL.bit.HSPCLKDIV = 0;//TB_DIV1;
ePWM_Regs[ch]->CMPCTL.bit.SHDWAMODE = 0;//CC_SHADOW;
ePWM_Regs[ch]->CMPCTL.bit.SHDWBMODE = 0;//CC_SHADOW;
ePWM_Regs[ch]->CMPCTL.bit.LOADAMODE = 0;//CC_CTR_ZERO;
ePWM_Regs[ch]->CMPCTL.bit.LOADBMODE = 0;//CC_CTR_ZERO;
ePWM_Regs[ch]->DBCTL.bit.IN_MODE = 2;//DBA_RED_DBB_FED;
ePWM_Regs[ch]->DBCTL.bit.POLSEL = 2;//DB_ACTV_HIC;
ePWM_Regs[ch]->DBCTL.bit.OUT_MODE = 3;//DB_FULL_ENABLE;
----------------------------------------------------------------------------------------
//phase shift setting
if(phase == 0) ePWM_Regs[ch]->TBPHS.bit.TBPHS = 0;
else if(phase > 0){
ePWM_Regs[ch]->TBCTL.bit.PHSDIR = 0;
ePWM_Regs[ch]->TBPHS.bit.TBPHS = (int16)((float32)ePWM_Regs[ch]->TBPRD * phase * 0.00277777);
}
else {
ePWM_Regs[ch]->TBCTL.bit.PHSDIR = 1;
ePWM_Regs[ch]->TBPHS.bit.TBPHS = (int16)((float32)ePWM_Regs[ch]->TBPRD * -phase * 0.00277777);
}
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//duty setting
ePWM_Regs[ch]->CMPA.bit.CMPA = (Uint32)((float32)ePWM_Regs[ch]->TBPRD * duty);
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Hi Allison,
I draw diagram regarding the timing you mentioned. Is this what you were looking for?
First, let me explain the diagram. I use up-down counter for EPWM. Black up-down counter is EPWM1 and pink one is EPWM3. EPWM3 is phase shifted by TBPHS regarding to EPWM1. And red one is CMPA and Blue one is Phase. Green one is TBPHS.
I use fixed frequency, 150kHz. So TBPRD is fixed. I change only phase and duty cycle. But phase and duty cycle are not fixed they are variable by time and controller.EPWM3A and EPWM3B is switching complimentary. TBPHS is Full-Wave of Phase. I make TBPHS full wave of Phase (TBPHS= -Phase), PHSDIR=1 when Phase<0. And when Phase>0 I set TBPHS=Phase , PHSDIR=0.
While drawing it, I understood that issues related to timing could lead to duty cycle problems. When sync in, TBPHS is updated and TBCTR and CMPA could not match. However, I'm unsure about the solution. Could you provide guidance on the next steps?
I knew there are library examples. But I didn't know there are C2000 bitfield examples. I'll find and apply directly. Thank you so much.
Best Regards,
Song
Hi Song,
I understand "If the count direction on a SYNC event is up and TBPHS is larger than CMPA" --> this make problem. because it make PWM turn on missing Action Qualifier. Is it right?
Yes, this is correct. Below I also sketched a quick, simple case of how a missing action can occur (the below example has the counter count down after a sync event) similar to your sketch earlier. You can see where the red CMPAD event is skipped because the TBCTR jumps over CMPA when the green SYNC pulse occurs:
Also apologies, yes I should have clarified that in order to implement T1 in a system where you are constantly updating TBPHS and CMPA (such as in your case), you would need to enable and disable T1 via software by comparing TBPHS and CMPA values during each period similar to what you are doing in the code you attached.
Looking at your code, though, it seems you are adjusting CMPA and CMPB instead of using the T1 event. Was that intentional? I would recommend you configure the T1 event event of the Action Qualifier submodule - see TRM Action Qualifier section descriptions. You can select EPWMxSYNCI as the T1 event source. Then you can set the necessary action in your if/else loops depending on the TBPHS and CMPA. In this way, the action from a T1 event would supplement what the missing CMPA action would have done. Let me know if you need more clarification here.
Best Regards,
Allison
