TMS320F28379D: PWM for Double Pulse Test

I am trying to generate a suitable double pulse for a double pulse test setup. I am trying to generate the double pulse using CMPA and CMPB within one TBCTR cycle and freeze the Time Base Counter (TBCTR) after one cycle so that the double pulse will not be repeated. But I am getting oscilloscope results as shown below, 

The code for the DPT PWM is as shown below, 

#include "F28x_Project.h"
void Gpio_select(void);
void Setup_ePWM(void);//PWM setup function
Uint16 TBPrd = 224;
Uint16 DB = 5;
float D1 = 0.8;
float D2 = 0.1;
void main(void)
{
InitSysCtrl();
DINT;
Gpio_select();

//enable PWM1, PWM2
CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;

//Initialize the Device Peripherals:
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;

Setup_ePWM();//Initialise PWM

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;

while(1)
{
}
}

void Gpio_select(void)
{
EALLOW;
InitEPwm4Gpio();
InitEPwm5Gpio();
GPIO_SetupPinOptions(31, GPIO_OUTPUT, GPIO_ASYNC);
GPIO_SetupPinOptions(34, GPIO_OUTPUT, GPIO_ASYNC);
EDIS;
}

void Setup_ePWM(void)
{
//Initializing Time Based Submodule
EALLOW;

EPwm4Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm4Regs.TBCTL.bit.CTRMODE = 2; // up down count - mode
EPwm4Regs.TBCTR = 0;//Clear Counter
EPwm4Regs.TBCTL.bit.PRDLD = 1;//Immediate Load of TBPRD into TBCTR
EPwm4Regs.TBPRD = TBPrd;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 1;
//Setup shadowing
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADAMODE = 1;
EPwm4Regs.CMPA.bit.CMPA = D1*TBPrd;
EPwm4Regs.CMPB.bit.CMPB = (1 - D2)*TBPrd;
//Initializing Action Qualifier Module
EPwm4Regs.AQCTLA.bit.ZRO = 2;//SET HIGH(2) ON UP COUNT(U) AT ZRO
EPwm4Regs.AQCTLA.bit.CAU = 1;//SET LOW(1) ON UP COUNT(U) AT CMPA
EPwm4Regs.AQCTLA.bit.PRD = 2;//SET HIGH(2) ON DOWN COUNT(D) AT PRD
EPwm4Regs.AQCTLA.bit.CBD = 1;//SET LOW(1) ON DOWN COUNT(D) AT PRD
//Initializing One Shot Trip
EPwm4Regs.TZCLR.bit.OST = 1;

EPwm5Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm5Regs.TBCTL.bit.CTRMODE = 2; // up down count - mode
EPwm5Regs.TBCTR = 0;//Clear Counter
EPwm5Regs.TBCTL.bit.PRDLD = 1;//Immediate Load of TBPRD into TBCTR
EPwm5Regs.TBPRD = TBPrd;
EPwm5Regs.TBCTL.bit.FREE_SOFT = 1;
//Setup shadowing
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 1;
EPwm5Regs.CMPA.bit.CMPA = D1*TBPrd + DB;
EPwm5Regs.CMPB.bit.CMPB = TBPrd - DB;
//Initializing Action Qualifier Module
EPwm5Regs.AQCTLA.bit.ZRO = 1;//SET LOW(1) ON UP COUNT(U) AT ZRO
EPwm5Regs.AQCTLA.bit.CAU = 2;//SET HIGH(2) ON UP COUNT(U) AT CMPA
EPwm5Regs.AQCTLA.bit.CBU = 1;//SET LOW(1) ON UP COUNT(U) AT CMPB
//Initializing One Shot Trip
EPwm5Regs.TZCLR.bit.OST = 1;

EDIS;
}